Industrial Technology Research Institute

Chi-Lung Wang

Chien-Hong Lin

Tzu-Fang Lee

Yung-Cheng Ma

Chih-Lung Chen

Chung-Hsien Wu

Yi-Ping You

Jing-Shan Liang

I-Yen Chen

Jeng Kuen Lee

Kuo Yu Chuang

Ren-Kewi Yang

Shin-Hung Kao

Kai-Chung Hsueh

Chin-Tsing Deng

Yen-Tun Peng

Chung Wen Huang

Tengh-Yih Wang

Hsien-Feng Kuo

Zong-Yau Yin

A configurable processing apparatus includes a plurality of processing units, at least an instruction synchronization control circuit, and at least a configuration memory. Each processing apparatus has a stall-output signal generating circuit to output a stall-output signal, wherein the stall-output signal indicates that an unexpected stall is occurred in the processing unit. The processing unit has a stall-in signal, and an external circuit of the processing unit can control whether the processing unit is stalled according to the stall-in signal. The instruction synchronization control circuit generates the stall-in signals to the processing units in response to a content stored in the configuration memory and the stall-output signals of the processing units, so as to determine operation modes and instruction synchronization of the processing units.

Configurable processing apparatus and system thereof

Disclosed is directed to a speed-level calculator and calculating method for dynamic voltage scaling. The speed-level calculator comprises a deadline counter, a shifter, and a fixed-point multiplier. The deadline counter calculates the residual time D from current time to each task deadline for completing an episode. The shifter generates a D' value by shifting the D value to the right for e-m bits, and takes the decimal fraction part of the D&#x2032; value for m bits. The speed-level calculator further comprises a saturation control circuit to detect if an overflow occurs on the D&#x2032; value. According to a pre-calculated parameter &#x3b1;corresponding to each task T, the fixed-point multiplier performs the multiplication of D&#x2032; and &#x3b1;. After completing saturation and rounding on the multiplication result, a corresponding clock period is generated by taking the integer part. This clock period is used as speed-level to switch the processor voltage and frequency.

Speed-level calculator and calculating method for dynamic voltage scaling

A memory device and a refresh method are provided herein. The memory device includes a memory array having memory rows. When an array refresh strobe (ARS) signal is received, it is determined whether the memory rows are required to be refreshed according to tag flags and reset statuses corresponding to the memory rows. When a row refresh strobe (RRS) signal is received, it is determined whether to refresh one of the memory rows according to a plurality of parameters including a value of a row to refresh counter, a value of a refresh deadline counter and/or a queue. When it is decided to start a refresh operation, one of the memory rows is selected according to the tag flag and the status, and the status of the selected memory row is updated after the selected memory row is refreshed.

Memory device and refresh method thereof

A method of power-gating instruction scheduling for leakage power reduction comprises receiving a program, generating a control-flow graph dividing the program into a plurality of blocks, analyzing utilization of power-gated components of a processor executing the program, generating the first power-gating instruction placement comprising power-off instructions and power-on instructions to shut down the inactive power-gated components, generating the second power-gating instruction placement by merging the power-off instructions as one compound power-off instruction and merging the power-on instructions as one compound power-on instruction, and inserting power-gating instructions into the program in accordance with the second power-gating instruction placement.

Power-gating instruction scheduling for power leakage reduction

An apparatus for switchable conditional execution in a VLIW processor is provided, comprising one or more decoders, one or more ALU with control units, and a register file. The decoder loads and decodes instructions from a fetch unit for decoding and sending the decoded instructions to the ALU with control units for execution. The register file stores and forwards the results on result buses to the decoders. The execution of a VLIW instruction includes a fetch stage, a decode stage, plural execution stages and a write-back stage. The invention has the features of approximate ASIC timing by conditional write-back with the compiler support for the conditional write-back, condition resolved just before write-back, software selective conditional issue and conditional write-back modes, and without hardware interlock/dependence checking for the VLIW processor.

Apparatus and method for switchable conditional execution in a VLIW processor

A demosaicking method and apparatus for color filter array interpolation in digital image acquisition systems is provided. The method includes a data-training phase and a data-practice phase. In the data-training phase of this invention, a huge volume of image samples are received for statistical analysis and compared with their corresponding full-color images. The optimal samples are then recorded in a database. In the data-practice phase of this invention, the images of color filter array are reconstructed. The present invention not only significantly improves the image quality but also reduces undue hardware cost. Furthermore, it has an advantage of ease of hardware implementation. All the color relationships of neighboring pixels are recorded in a database for statistical analysis. The database is not limited to only one set. It is also pretty flexible, and can be adjusted or updated depending on desired applications.

Demosaicking method and apparatus for color filter array interpolation in digital image acquisition systems

An implementation method is described that efficiently achieves Quality-of-Service (QoS) criteria in a Media-on-Demand (MOD) server system. A MOD server system comprises a media server connected to a plurality of client stations via a shared transmission medium, such as a LAN network. To guarantee the QoS, the output rate of each data stream (of data requested by a client) needs to be specified individually. The inventive timer interrupt driven method achieves the necessary QoS, while reducing the complexity of conventional systems. In particular, a set of hardware timers is used to control the data rates. Each data request is handled by an individual timer, hence, different data streams may have different data request rates. Such design provides several advantages over other implementations, such as low overhead and high scalability.

Timer Interrupt method for achieving quality-of-service criteria in a

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Hsinchu, Taiwan

Chi-Lung Wang