Semiconductor Manufacturing International (shanghai) Corporation

Cathay R&d Center Co., Ltd

Cathay Industrial Biotech Ltd.

Chi Liu

Ta Lee Yu

Quan Li

Talee Yu

Jing Liu

Bingbing Qin

Naiqiang Li

Yi Zheng

Xiwei Yang

Disclosed is a process for treating a reaction solution containing a long chain dicarboxylate. The process is characterized by comprising: acidifying a reaction solution so as to convert the long chain dicarboxylate into a long chain dicarboxylic acid, adding an extractant so as to extract the resulting long chain dicarboxylic acid, separating the phase rich in the long chain dicarboxylic acid, and further separating the long chain dicarboxylic acid. The process of the present invention has the following advantages: 1) the processing route is simple, the operation time is short, less equipment is required, and the production efficiency is high; 2) product yield is high; 3) product quality is good, purity in the resulting products is high, and the color is lighter; and 4) no active carbon is consumed and the solvent can be recycled, thereby saving resources and being environmentally friendly.

Process for treating reaction solution containing long chain dicarboxylate

A semiconductor device for ESD protection includes a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed within the substrate. The well region is characterized by a first depth. The device includes an MOS transistor, a first bipolar transistor, and a second bipolar transistor. The MOS transistor includes a first lightly doped drain (LDD) region of a second depth within the well region, and a drain region and an emitter region within in the first LDD region. The emitter region is characterized by a second conductivity type. The first bipolar transistor is associated with the emitter region, the first LDD region, and the well region, and is characterized by a first trigger voltage. The second bipolar transistor is associated with the first LDD region, the well region, and the substrate, and is characterized by a second trigger voltage.

Integrated electrostatic discharge (ESD) device

A method for making a semiconductor device includes providing a substrate of a first conductivity type and having a surface region, forming a well region of a second conductivity type and having a first depth in the substrate, adding a gate dielectric layer overlying the surface region, adding a gate layer overlying the gate dielectric layer, forming a first LDD region of the first conductivity type and having a second depth within the well region, forming an emitter region of the second conductivity type within the first LDD region, and forming a second LDD region of the first conductivity type with the well region, a channel region separates the first and second LDD regions. The method further includes forming a source region being of the first conductivity type within the second LDD region and adding an output pad coupled to both the drain and emitter regions.

An integrated circuit device comprising an improved bonding pad structure. The device has a semiconductor substrate. A plurality of active MOS devices are formed on the semiconductor substrate. The device has an interlayer dielectric layer overlying the plurality of active MOS devices and at least one single metal bonding pad formed on the interlayer dielectric layer and directly over at least one of the active devices. At least four edge regions are formed on a square shape of the at least one single metal bonding pad. An angled cut region is formed on each of the four edge regions. The device has a buffer metal layer free region located between the plurality of active MOS devices and the at least one single metal bonding pad. The buffer metal layer free region does not have a buffer metal layer in the interlayer dielectric layer.

Device under bonding pad using single metallization

An ESD device includes a first and second well regions disposed in a semiconductor substrate. The first well region comprises a plurality of N wells spaced at a predetermined length. A heavily doped P+ region and a heavily doped N+ region are disposed in each of the N wells. The heavily doped N+ region is coupled to Vdd and a heavily doped P+ region in an N well is electrically coupled to the heavily doped N+ region in an adjacent N well. The second well region comprises a P well abutting an N well. A heavily doped P+ region and a heavily doped N+ region are disposed in the P well. The heavily doped N+ region in the P well is electrically coupled to the heavily doped P+ region of the adjacent N well in common with an I/O circuit, and the heavily doped P+ region is coupled to Vss.

Device and methods for electrostatic discharge protection

Techniques for ESD protection are provided. An ESD protection device includes a first well region and a second well region disposed in a semiconductor substrate, with an isolation region therebetween. N+ implant regions are disposed in the second well region and are coupled in common at a first node. NLDD regions are disposed between the N+ implant regions, and pocket implants underlie each of the NLDD regions. Current discharge paths are defined by corresponding NLDD regions and pocket implants when a voltage of the first node exceeds a breakdown voltage. In a specific embodiment, the breakdown voltage is less than a breakdown voltage for a logic gate oxide.

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Shanghai, China

Chi Liu