Taiwan Semiconductor Manufacturing Comp. Ltd.

Chi-Lin Liu

Shang-Chih Hsieh

Lee-Chung Lu

Jerry Chang-Jui Kao

Hui-Zhong Zhuang

Wei-Hsiang Ma

Cheok-Kei Lei

Jerry Chang Jui Kao

Zhe-Wei Jiang

Chi-Yu Lu

Kai-Chi Huang

Yung-Chen Chien

Ting-Wei Chiang

Stefan Rusu

Chang-Yu Wu

Po-Chia Lai

Che Min Huang

Greg Gruber

Sheng-Hsiung Chen

Fong-yuan Chang

Meng-Hung Shen

Yan-Hao Chen

Yi-Hsin Ko

Ming-Chang Kuo

Yu-Chi Li

Chia-Wei Tseng

Li-Chun Tien

Chung-Cheng Chou

Ta-Pen Guo

Jung-Chan Yang

Tzu-Ying Lin

Jian-Sing Li

Yi-Hsun Chen

Chien-Hsing Li

Sang Hoo Dhong

Yi-Tzu Chen

Cheng-Chung Lin

Xiangdong Chen

Hsueh-Chih Chou

Chia Hao Tu

Seid Hadi Rasouli

Meng-Hsueh Wang

Yu-Jheng Ou-Yang

Yangsyu Lin

Jung-chan Yang

Ji-Yung Lin

Hsiao Wen Lu

Henry Huang

Shang-chih Hsieh

Bor-Tyng Lin

Yung-Chen Chen

A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.

Low-power flip flop circuit

The present disclosure provides a semiconductor device which includes a multiplexer, a master latch, and a slave latch. The multiplexer outputs an inverse of an input data signal or an inverse scan input signal according to a scan enable signal. The master latch is coupled to an output terminal of the multiplexer, and is configured to latch the inverse of the input data signal based on an input clock signal in response to the scan enable signal being in a low-logic state. The slave latch is coupled to the output terminal of the multiplexer through a first clocked CMOS inverter, and is configured to receive the input data signal and to output a latched slave latch data based on the input clock signal. A leakage-free dummy cell is disposed in a non-critical path of the master latch and the slave latch.

Leakage-free dummy cell for semiconductor devices

A circuit includes a multi-bit flip flop, an integrated clock gating circuit connected to the multi-bit flip flop, and a control circuit connected to the integrated clock gating circuit and the multi-bit flip flop. The control circuit compares output data of the multi-bit flip flop corresponding to input data with the input data. The control circuit generates an enable signal based on comparing the output data of the multi-bit flip flop corresponding to the input data with the input data of the multi-bit flip flop. The control circuit provides the enable signal to the integrated clock gating circuit, wherein the integrated clock gating circuit provides, based on the enable signal, a clock signal to the multi-bit flip flop causing the multi-bit flip flop to toggle.

Multi-bit flip flop

A circuit includes a first power node having a first voltage level, a second power node having a second voltage level different from the first voltage level, a reference node having a reference voltage level, a master latch that outputs a first bit based on a received bit, a slave latch that outputs a second bit based on the first bit and an output bit based on a selected one of the first bit or a third bit, a first level shifter that outputs the third bit based on a complementary bit pair, and a retention latch including a second level shifter and a pair of inverters that outputs the complementary bit pair based on the second bit. The slave latch and the first level shifter are coupled between the first power and reference nodes, and the retention latch is coupled between the second power and reference nodes.

Data retention circuit and method

An integrated circuit includes a flip-flop circuit and a gating circuit. The flip-flop circuit is arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode. The gating circuit is arranged for generating the first clock signal and the second clock signal according to the master signal and an input clock signal. When the input clock signal is at a signal level, the first clock signal and the second clock signal are at different logic levels. When the input clock signal is at another signal level, the first clock signal and the second clock signal are at a same logic level determined according to a signal level of the master signal.

Flip-flop device and method of operating flip-flop device

A logic circuit (for providing a multibit flip-flop (MBFF) function) includes: a first inverter to receive a clock signal and generate a corresponding clock_bar signal; a second inverter to receive the clock_bar signal and generate a corresponding clock_bar_bar signal; a third inverter to receive a control signal and generate a corresponding control_bar signal; and a series-chain of 1-bit transfer flip-flop (TXFF) circuits, each including: a NAND circuit to receive data signals; and a 1-bit transmit gate flip-flop (TGFF) circuit to output signals Q and q, and receive an output of the NAND circuit, the signal q from the TGFF circuit of a preceding TXFF circuit in the series-chain, the clock_bar and clock_bar_bar signals, and the control and control_bar signals; and the first transfer TXFF circuit in the series-chain being configured to receive a start signal in place of the signal q from an otherwise preceding TGFF circuit.

Logic circuits with reduced transistor counts

A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.

Multiplexer

Disclosed herein are embodiments related to a power efficient multi-bit storage system. In one configuration, the multi-bit storage system includes a first storage circuit, a second storage circuit, a prediction circuit, and a clock gating circuit. In one aspect, the first storage circuit updates a first output bit according to a first input bit, in response to a trigger signal, and the second storage circuit updates a second output bit according to a second input bit, in response to the trigger signal. In one aspect, the prediction circuit generates a trigger enable signal indicating whether at least one of the first output bit or the second output bit is predicted to change a state. In one aspect, the clock gating circuit generates the trigger signal based on the trigger enable signal.

Power efficient multi-bit storage system

A clock gating circuit includes an input circuit, a cross-coupled pair of transistors, a first transistor of a first type and a first pull-up transistor of the first type. The input circuit is configured to set a first control signal of a first node in response to a first or second enable signal. The cross-coupled pair of transistors is coupled between the first node and an output node. The first transistor is coupled between the first and a second node. The first pull-up transistor includes a first gate terminal, a first drain terminal and a first source terminal. The first gate terminal is configured to receive an inverted clock input signal. The first drain terminal is coupled to the second node and the first transistor. The first pull-up transistor is configured to adjust a clock output signal responsive to the inverted clock input signal.

Clock gating circuit and method of operating the same

The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in a layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.

Metal cut optimization for standard cells

A method of modifying an integrated circuit layout includes determining whether a first conductive line and a second conductive line are subject to a parasitic capacitance above a parasitic capacitance threshold. The method further includes adjusting the integrated circuit layout by moving the first conductive line in the integrated circuit layout in response to determining to move the first conductive line. The method further includes inserting an isolation structure between the first and second conductive lines in the integrated circuit layout in response to determining not to move the first conductive line.

Capacitive isolation structure insert for reversed signals

In some embodiments, a flip-flop is disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate. The flip-flop includes a first clock inverter circuit that resides within the flip-flop region, and a second clock inverter circuit residing within the flip-flop region. The first clock inverter circuit and the second clock inverter circuit are disposed on a first line. Master switch circuitry is made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region of the integrated circuit layout. The master switch circuitry and the first clock inverter circuit are disposed on a second line perpendicular to the first line. Slave switch circuitry is operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter. The slave switch circuitry and the second clock inverter circuit are disposed on a third line that is in parallel with and spaced apart from the second line.

Flip-flop with delineated layout for reduced footprint

A clock gating circuit includes a NOR logic gate, a transmission gate, a cross-coupled pair of transistors, and a first transistor. The NOR logic gate is coupled to a first node, and receives a first and a second enable signal, and outputs a first control signal. The transmission gate is coupled between the first and a second node, and receives the first control signal, an inverted clock input signal and a clock output signal. The cross-coupled pair of transistors is coupled between the second node and an output node, and receives at least a second control signal. The first transistor includes a first gate terminal configured to receive the inverted clock input signal, a first drain terminal coupled to the output node, and a first source terminal coupled to a reference voltage supply. The first transistor adjusts the clock output signal responsive to the inverted clock input signal.

Growing community of inventors

Taipei, Taiwan

Chi-Lin Liu