Sandisk Technologies Inc.

Chi-Lin Hsu

Yan Li

Tai-Yuan Tseng

Hiroyuki Mizukoshi

A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable microcontroller. The microcontroller has a first processor that executes instructions to coordinate sequences of voltages applied to the memory structure by a first circuit in order to perform memory operations. The microcontroller has a second processor that executes second instructions to control a second circuit to test conditions of the non-volatile memory cells in response to the voltages applied to the memory structure. The microcontroller may have a third processor that controls the flow of the memory operation and directs the first and second processors to execute the instructions. The instructions of the various processors may be updated, which provides for flexible flow, core operation control, and condition testing.

Microcontroller architecture for non-volatile memory

An apparatus includes a first processor that generates first control signals to control a first circuit to perform memory operations on memory cells. A first number of first physical signal lines delivers the first control signals to a conversion circuit. A second number of second physical signal lines delivers converted control signals to the first circuit. The conversion circuit is coupled by the first number of first physical signal lines to the first processor and by the second number of second physical signal lines to the first circuit. The conversion circuit converts the first control signals to the converted control signals, and outputs the converted control signals to the first circuit. The first number of first physical signal lines is less than the second number of second physical signal lines to reduce the first number of first physical signal lines coupled between the first processor and the first circuit.

Signal reduction in a microcontroller architecture for non-volatile memory

An apparatus is provided that includes a processor and an instruction memory including a first memory, a second memory, a third memory and an instruction selector circuit. The first memory is configured to receive a first instruction address from the processor, the second memory is configured to receive the first instruction address from the processor and generate a control signal based on the received first instruction address, and the third memory is configured to receive the first instruction address from the processor. The instruction selector circuit is configured to selectively send an instruction from one of the first memory and the third memory based on the control signal to the processor, and to selectively enable and disable the third memory to reduce power consumption of the instruction memory.

Microcontroller instruction memory architecture for non-volatile memory

A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable hybrid microcontroller having a state machine and one or more processors. The state machine is configured to generate a first set of execution signals in response to a request to perform memory operations on non-volatile memory cells in the memory system. The first set of execution signals have a format configured to interface with one or more circuits coupled to the non-volatile memory cells. The hybrid microcontroller has an interface that translates the first set of execution signals to instruction identifiers. The one or more processors execute instructions identified by the instruction identifiers to generate a second set of execution signals. The second set of execution signals are provided to the one or more circuits to perform the memory operations on the non-volatile memory cells.

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San Jose, CA, United States of America

Chi-Lin Hsu