Industrial Technology Research Institute

Chi-Lin Chen

Yu-Cheng Chen

Jung-Fang Chang

Hung-Tse Chen

Jia-Xing Lin

Liang-Tang Wang

Shun-Fa Huang

Po-Tsun Liu

Cheng-Chung Chen

Chi-Shen Lee

Hsing-Hua Wu

Chich-Shang Chang

Chi-Ming Chang

I-Hsuan Peng

Yung-Hui Yeh

Yung-Fu Wu

Chai-Yuan Sheu

Lung-Pin Hsin

Chin-Jen Huang

Ching-Hsuan Tang

Yih-Rong Luo

Yu-Lung Liu

Chiung-Wei Lin

A multi-layered complementary conductive line structure, a manufacturing method thereof and a manufacturing method of a TFT (thin film transistor) display array are provided. The process of TFT having multi-layered complementary conductive line structures does not need to increase the mask number in comparison with the currently process and is able to solve the resistance problem of the lines inside a display.

Multi-layered complementary conductive line structure

A method of fabricating a thin film transistor (TFT) includes first providing a strip-shaped silicon island which is a thin film region with a predetermined long side and short side. Next, the strip-shaped silicon island is subject to an ion implantation to form a first ion doping region and a second ion doping region. The first and second ion doping regions, respectively used as the source and the drain of the TFT, are located at two sides along the long side of the island and substantially perpendicular to the gate. A gate is formed over the strip-shaped silicon island and the first and second ion doping regions, wherein the gate is substantially parallel to the direction of the short side.

Method of fabricating thin film transistor structure having strip-shaped silicon island

A memory cell suitable for being disposed over a substrate is provided. The memory cell includes a poly-silicon island, a first dielectric layer, a trapping layer, a second dielectric layer and a control gate. The poly-silicon island is disposed on the substrate and includes a source region, a drain region and a channel region located between the source and drain regions. The channel region has a plurality of regularly arranged tips thereon. The first dielectric layer is disposed on the poly-silicon island. The trapping layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the trapping layer. The control gate is disposed on the second dielectric layer. The memory cell mentioned above can be integrated into the LTPS-LCD panel or OLED panel.

Pixel structure

A structure of a thin film transistor and a method for making the same are provided. The structure includes a strip-shaped silicon island, a gate, and a first and second ion doping regions. The strip-shaped silicon island is a thin film region with a predetermined long side and short side, and farther has a plurality of lateral grain boundaries substantially parallel to the short side of the silicon island. The gate is located over the silicon island and substantially parallel to the lateral grain boundaries. The first and second ion doping regions, used as source/drain regions of the TFT, are located at two sides along the long side of the island and substantially perpendicular to the gate.

Thin film transistor structure

A method for fabricating a semiconductor device includes providing a substrate, forming an amorphous silicon layer over the substrate, forming a heat retaining layer on the amorphous silicon layer, patterning the heat retaining layer, and irradiating the patterned heat retaining layer.

Method of semiconductor thin film crystallization and semiconductor device fabrication

A method for forming a polysilicon film in a plasma-assisted chemical vapor deposition (CVD) system including a chamber in which a first electrode and a second electrode spaced apart from the first electrode are provided comprises providing a substrate on the second electrode, the substrate including a surface exposed to the first electrode, applying a first power to the first electrode for generating a plasma in the chamber, applying a second power to the second electrode during a nucleation stage of the polysilicon film for ion bombarding the surface of the substrate, and flowing an erosive gas into the chamber.

Method of direct deposition of polycrystalline silicon

Fabrication process of memory cell

A heat sink layer is formed on portions of a substrate, and then an amorphous silicon layer is formed thereon. The heat coefficient of the sink layer is greater than that of the substrate. When an excimer laser heats the amorphous silicon layer to crystallize the amorphous silicon, nucleation sites are formed in the amorphous silicon layer on the heat sink layer. Next, laterally expanding crystallization occurs in the amorphous silicon layer on the substrate to form polysilicon having a crystal size of a micrometer.

Method of controlling polysilicon crystallization

A method of forming poly-silicon thin film transistors is described. An amorphous silicon thin film transistor is formed on a substrate, and then the Infrared (IR) heating process is used. A gate metal and source/drain metal are heated rapidly, and conduct heat energy to an amorphous silicon layer. Next, crystallization occurs in the amorphous silicon layer to form poly-silicon. Therefore a poly-silicon thin film transistor is produced.

Method of forming poly-silicon thin film transistors

Memory cell, pixel structure and fabrication process of memory cell

Multi-layered complementary conductive line structure and manufacturing method thereof and manufacturing method of a thin film transistor display array

A method for manufacturing a flexible panel is disclosed, which has the following steps. First, a first substrate having a plurality of functional switches or conducting lines thereon is provided. Then, a second substrate is bonded on the functional switches or conducting lines, and the first substrate is thinned to a predetermined thickness subsequently. Afterwards, a flexible third substrate is adhered on the first substrate, wherein the first substrate is sandwiched between the second substrate and the third substrate. Finally, the second substrate is removed.

Method for manufacturing a flexible panel for a flat panel display

The present invention discloses an active organic light emitting diode (AOLED) display structure. A color filter and thin film transistor organic light emitting diode (TFT-OLED) are incorporated on one substrate of the AOLED. Moreover, a Indium Tin Oxide(ITO)layer of the AOLED is deposited with a black matrix layer so as to lower light leakage effect and increase the contrast and color purity level in between pixels of the display. By adopting such technology, a flat panel display having large area, high resolution and low product cost is accordingly implemented.

Active organic light emitting diode display structure

A method of manufacturing a TFT array panel for a LCD disclosers that the gate electrode wiring, transparent conducting electrode, and the first electrode of the storage capacity are formed while the first mask is processing. Then, the selective deposition method is used to process the growth of the first metal wiring. This, therefore, can reduce the numbers of the mask processes. Further, the metal deposition with photo-resist lift-off step is used to implement the layout of the second metal wiring for the consequent transmission lines in the manufacturing process. Finally, the process of the passivation layer deposition is used to implement associated circuits of a TFT array panel for a LCD. The TFT array panel for a LCD for manufacturing circuits can simplify the manufacturing process and reduce the cost.

Method of manufacturing a TFT array panel for a LCD

A multi-layered wire structure includes a substrate, a plurality of first conductive lines formed in a first layer over the substrate extending in parallel to each other in a first direction, a plurality of second conductive lines formed in a second layer over the first layer extending in parallel to each other in a second direction orthogonal to the first direction, a plurality of sets of third conductive lines formed in the second layer extending in the first direction, each set of third conductive lines corresponding to one of the first conductive lines, and a plurality of sets of conductive paths formed between the first layer and the second layer, each set of conductive paths corresponding to one of the first conductive lines and one set of third conductive lines and electrically connecting the corresponding first conductive line to the corresponding set of third conductive lines.

Growing community of inventors

Hsinchu, Taiwan

Chi-Lin Chen