Marvell International Limited

Chi-Kuang Chen

Li Sha

Ching-Han Tsai

Yaojun Luo

Guan-Ming Su

Hongjie Guan

Junqiang Lan

Tzun-Wei Lee

Ye Zhou

In accordance with the teachings described herein, systems and methods are provided for advanced execution of branch instructions in a microprocessor pipeline. In one embodiment, a branch instruction of an assembly language program code is executed that includes (i) a condition operand, (ii) a branch destination operand, and (iii) a program count operand. It is determined whether a current program count matches a stored program count operand. After determining that a condition was met when the branch instruction was executed, and in response to determining that the current program count matches the stored program count operand, a destination instruction specified by the stored branch destination operand is fetched.

Early execution of conditional branch instruction with pc operand at which point target is fetched

This disclosure describes tools capable of generating messages for use in deblocking filtering a video stream, the messages based on prediction parameters extracted from the video stream.

Deblocking filtering

Devices, systems, methods, and other embodiments associated with decoding image data are described. In one embodiment, an apparatus decoding a bitstream includes a parser that parses a command that includes instructions for decoding a syntax element bitstream from the bitstream. The parser functions to identify a number times to repeat the command and to identify a table associated with the syntax element bitstream based, at least in part, on a table identification (ID) in the command. A decoder decodes the syntax element bitstream as specified by the command based, at least in part, on retrieving a value in a table associated with the table ID to generate a syntax element.

Decoding image data

Devices, systems, methods, and other embodiments associated with a buffer controller are described. In one embodiment, an apparatus includes a buffer to buffer data. The apparatus further includes a status register and control logic. The control logic at least processes write commands. When the buffer is full and a write command to write data to the buffer is received, the control logic is configured to: accept the data without writing the data to the buffer, send an acknowledgment that the buffer was written, and set an overflow bit in the status register.

Buffer controller

In one embodiment the present invention includes a microprocessor that has a pipeline circuit, a branch circuit, and a control circuit. The pipeline circuit pipelines instructions for the microprocessor. The branch circuit is coupled to the pipeline circuit and operates to store branch information. The control circuit is coupled to the pipeline circuit and the branch circuit. The control circuit stores a first branch information from the pipeline circuit to the branch circuit when a first condition is met. The control circuit retrieves a second branch information from the branch stack circuit to the pipeline circuit when a second condition is met. In this manner, the need for dedicated pipeline flush circuitry is avoided.

Execution of conditional branch instruction specifying branch point operand to be stored in jump stack with branch destination for jumping to upon matching program counter value

Growing community of inventors

Santa Clara, CA, United States of America

Chi-Kuang Chen