Marvellworld Trade Ltd.

Marvell International Limited

Marvell World Travel Ltd.

Chi Kong Lee

Hyunsuk Shin

Tony Yoon

Jungil Park

Fei Sun

Masayuki Urabe

Siu-Hung Frederick Au

Akio Goto

Chih-Ching Chen

Siu-Hung Fred Au

Xueshi Yang

Wei Xu

Jinjin He

Xueting Yu

Systems, methods and computer program products for programming data into a multi-plane memory device employ a multi-plane data order. To allow multiple data pages to be programmed without a need to increase the size of page buffers, in some implementations, a data transfer scheme at which the data pages are programmed can be manipulated. Specifically, data across all channels can first be programmed into a first plane of the multi-plane flash memory device in parallel. While the data transfer program operation is in progress, data to be programmed into a succeeding plane (e.g., plane '1') can be read into and cached in one or more page buffers. After the data transfer program for the first plane is complete, data cached in the page buffers can be immediately latched and programmed into the multi-plane flash memory device.

Multi-plane data order

Devices, systems, methods, and other embodiments associated with selectively scheduling memory accesses in parallel are described. In one embodiment, a method includes determining, by a hardware controller, an access speed associated with a page request. The page request is a request to access a memory page in a memory device. The access speed is a number of clock cycles used to access the memory page addressed by the page request. The method also includes scheduling when the page request will be executed based, at least in part, on the access speed by assigning the page request to be executed in parallel with at least one other page request that is to access a different memory page in the memory device using a same number of clock cycles as the page request.

Selectively scheduling memory accesses in parallel based on access speeds of memory

In some implementations, a method includes receiving information in a storage device controller from one or more storage devices in a solid state drive system over one or more channels; and for information received over each of the one or more channels, determining whether a condition for sending the information received over the channel to a host device is satisfied, and sending the information received over the channel to the host device when the condition for sending the information is satisfied.

Flexible sequence design architecture for solid state memory controller

In some implementations, an apparatus includes a first programmable hardware timer that specifies an initial wait time before issuing two or more commands to a storage device, and a second programmable hardware timer that specifies an interval time between at least two commands of the two or more commands.

Storage device command interval controller

A system including a non-volatile semiconductor memory (NVSM), an interface module and a control module. The NVSM stores first and second blocks of data. The first or second block of data is non-page based such that a size of the first block of data or a size of the second block of data is not an integer multiple of a page of data. The interface module transfers the first and second blocks of data during respectively a first data transfer event and a second data transfer event. The control module, based on descriptors, controls the first and second data transfer events such that the interface module transfers the first block of data between the interface module and the NVSM while transferring the second block of data between the interface module and the NVSM. The descriptors include respective sets of instructions for transferring the first and second blocks of data.

Method and apparatus for parallel transfer of blocks of data between an interface module and a non-volatile semiconductor memory

Systems, methods, apparatus, and techniques are provided for processing data from a storage medium. A stripe of data stored on the storage medium is read, where the stripe comprises a plurality of data allocation units (AUs) and a parity AU. Error correction decoding is applied to each of the plurality of data AUs to produce a plurality of decoded data AUs. It is determined whether a value of the parity AU is satisfied by values of bytes in the plurality of decoded data AUs. The plurality of decoded data AUs are output in response to a determination that the value of the parity AU is satisfied by the values of bytes in the plurality of decoded data AUs.

Architecture for storage of data on NAND flash memory

The present disclosure includes systems and techniques relating to controlling memory devices with a generic command descriptor. In some implementations, an apparatus, systems, or methods can include a memory controller including an interface configured to connect with a NAND memory device and circuitry configured to receive a descriptor of a command sequence including multiple segments for managing the NAND memory device. The descriptor can include option information corresponding to each segment of the command sequence. The circuitry can also be configured to generate the command sequence for managing the NAND memory device based, at least in part, on the option information of the descriptor.

Generic command descriptor for controlling memory devices

The present disclosure includes systems and techniques relating to management of bit line errors based on a stored set of data. In some implementations, a system can include a device including non-volatile solid state memory and a memory controller. The memory controller can be configured to identify, from the solid state memory of the device, one or more bit line errors for the device upon power up of the system, construct a set of data corresponding to the one or more bit line errors for the device, store the set of data, at least in part, in the device, and, upon a subsequent power up of the system, identify the one or more bit line errors for the device from the stored set of data.

Management of bit line errors based on a stored set of data

Apparatus for programming a non-volatile memory, the apparatus having corresponding methods and tangible computer-readable media, comprise: a command memory configured to hold a plurality of command templates, wherein each of the command templates specifies a sequence of pad signals; a state machine configured to i) receive descriptors, wherein each of the descriptors includes a pointer to a respective one of the command templates in the command memory, and ii) generate the sequence of pad signals based on the command template indicated by the respective pointer; and a non-volatile memory interface configured to provide, to pads of the non-volatile memory, the sequence of pad signals generated by the state machine.

NAND flash controller with programmable command templates

A storage drive including first, second, third, fourth and fifth modules. The first module is configured to control transfer of blocks of data between a host device and the storage drive. The second module is configured to transfer the blocks of data to and from a non-volatile semiconductor memory in the storage drive. The third module is configured to generate a first descriptor, which describes a transfer of blocks of data between the second module and the non-volatile semiconductor memory. The fourth module is configured to, according to the first descriptor, generate second descriptors. Each of the second descriptors corresponds to a respective one of the blocks of data. The fifth module is configured to generate instruction signals based on the second descriptors. The second module is configured to, based on the instruction signals, transfer the blocks of data between the first module and the non-volatile semiconductor memory.

Apparatus and method for generating descriptors to transfer data to and from non-volatile semiconductor memory of a storage drive

Systems, methods, apparatus, and techniques are provided for writing data to a storage medium. A stripe of the storage medium is interfaced via one or more data transfer channels, where the stripe comprises a plurality of pages of the storage medium. A data stream is received and the data stream is portioned into a plurality of allocation units (AUs), where each AU in the plurality of AUs has a pre-determined byte length. A first portion of a selected AU from the plurality of AUs is written to a first page of the plurality of pages and a second portion of the selected AU is written to a second page of the plurality of pages by consecutively writing bytes of the selected AU from a starting byte on the first page to an ending byte on the second page.

Architecture to allow efficient storage of data on NAND flash memory

In accordance with an embodiment of the disclosure, systems and methods are provided for reducing an amount of peak power consumption in a device. In certain implementations, a first signal and a second signal are received, wherein the first signal and the second signal are indicative of amounts of power consumption in a device. The first signal is combined with the second signal to generate a combined signal, and at least a portion of the second signal is shifted in time to cause a combination of the first signal and the shifted portion to have a peak amplitude less than a peak amplitude of the combined signal.

Systems and methods for reducing peak power consumption in a solid state drive controller

A control system includes a control module configured to control data transfer events of blocks of data between an interface management module and a non-volatile semiconductor memory based on at least two descriptors for each one of the data transfer events. The non-volatile semiconductor memory is prepared for a read event or a program event of the data transfer event. The interface management module and the non-volatile semiconductor memory are configured to operate within a solid-state memory drive. A command management module is configured to generate a parameter signal based on the at least two descriptors. The interface management module is configured to generate instruction signals based on the parameter signal and transmit the instruction signals to the non-volatile semiconductor memory to perform the read event or the program event.

Interface management control systems and methods for non-volatile semiconductor memory

Methods, systems and computer program products for providing a sequencer that schedules job descriptors are described. The sequencer can manage the scheduling of the job descriptors for execution based on the availability of their respective segments and channels. For example, the sequencer can check the status of the segments, and identify one or more segments that are in busy or full state, or one or more segments that are in non-busy or empty state. Based on the status check, the sequencer can execute job descriptors out of order, and in particular, give priorities to job descriptors whose associated segments are available over job descriptors whose associated segments are in busy or full state.

Descriptor scheduler

Devices, systems, methods, and other embodiments associated with selectively scheduling memory accesses in parallel are described. In one embodiment, a method determines an access speed for a page request. The access speed is a number of clock cycles used to access a memory device of a group of memory devices. The page request is a request to access a memory page mapped to the memory device. Different page requests are selectively scheduled to access different memory devices in parallel. The different page requests access the different memory devices in a same number of clock cycles.

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Fremont, CA, United States of America

Chi Kong Lee