Nvidia Corporation

Intel Corporation

Chi Keung Lee

Narsing Krishna Vijayrao

Guillermo Juan Rozas

Sudarshan Kumar

Sridhar Krishnamurthy

Jay Chieh Chen

Binh Pham

Vikas Kumar Agrawal

Jason Golbus

Umang Shah

Kumar Sudarshan

Shrivathsa Bhargavravichandran

A dual-domain dynamic multiplexer and a method of transitioning between asynchronous voltage and frequency domains. One embodiment of the dual-domain dynamic multiplexer includes: (1) a first domain having a first voltage and a first clock, and a second domain having a second voltage and a second clock, (2) a plurality of data and data select input pairs wherein a data input of an input pair is in the first domain and a data select input of an input pair is in the second domain, and (3) a pre-charge stage in the second domain that is energized upon an edge of the second clock, whereby one data and data input pair is enabled and data latched in the second domain upon another edge of the second clock.

Dual-domain dynamic multiplexer and method of transitioning between asynchronous voltage and frequency domains

A technique for generating pushdown data comprises performing logical pushdown of circuit elements and nets and detecting physical pushdown based on partition boundary crossings. Geometry associated with one logical level may be used as a keep-out region for the same physical layer when generating physical design of a different logical level. The technique may advantageously enable concurrent design in both top-level and low-level physical design phases, thereby reducing overall design cycle time in developing an integrated circuit.

Hierarchical pushdown of cells and nets to any logical depth

In one embodiment, a microprocessor includes one or more processing cores. At least one processing core includes a clock shaping circuit that is configured to receive a clock input signal. The clock shaping circuit includes rising edge skew logic that is configured to selectively delay a rising edge of the clock input signal and falling edge skew logic that is configured to selectively delay a falling edge of the clock input signal independent of adjustment of the rising edge.

Glitchless programmable clock shaper

A method and apparatus to increase the performance of a floating point multiplier accumulator (FMAC). The method comprises receiving three floating point numbers and computing a product of the first floating point number and the second floating point number and adding a third floating point number to produce a sum value and a carry value. A propagate value, a kill value and a generate value are then computed based on the sum value and the carry value. Simultaneously the sum value is added to the carry value to create a first result, the sum value is added to the carry value and incremented by one to create a second result, the sum value is added to the carry value and incremented by two to create a third result, and a decimal point position is determined. One of the first result, the second result and the third result is then selected responsive to a rounding mode and the decimal point position. The selected result is normalized based on the decimal point position. The apparatus comprises a multiplier with a propagate, kill, generate generator (PKG generator) coupled to it. An adder, a plus-oner, a plus-two-er and a leading zero anticipator (LZA) are each coupled to the PKG generator in parallel. A rounding control unit is coupled to the LZA and coupled to a multiplexor that outputs a result from one of the adder, the plus-oner, and the plus-two-er responsive to the rounding control unit. A normalization shifter is coupled to the multiplexor and the LZA.

Method and apparatus for improving the performance of a floating point multiplier accumulator

The present invention relates to a new low-power, high performance multiplier circuit design, and more specifically to a partitioned multiplier implemented using a modified, symmetrical Wallace tree structure that enables the power to parts of the multiplier to be selectively turned on and off. A multiplier implemented using complementary pass-transistor logic (CPL) 3:2 carry save adders (CSAs) includes a left array with a first multiple of CPL CSAs, a right array with a second multiple of CPL CSAs, and a merge block coupled to the left array and the right array, such that the left and right arrays are not coupled to each other. The left and right arrays are configured to independently receive power, such that, each array can be turned on and off without affecting the other array. The merge block includes a third multiple of CPL CSAs and the merge block can be configured to output a result value of a multiplication operation.

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San Jose, CA, United States of America

Chi Keung Lee