Taiwan Semiconductor Manufacturing Comp. Ltd.

Chi-Kang Liu

Yu-Lien Huang

Chi-Wen Liu

Clement Hsingjen Wann

Chun-Hsiang Fan

Yung-Ta Li

Ming-Huan Tsai

Tsu-Hsiu Perng

Tung-Ying Lee

Ming-Hsi Yeh

Huan-Just Lin

Jr-Jung Lin

Hsin-Li Cheng

Han-Pin Chung

Sung-Hsun Wu

Hsiu-Hsiang Lin

Kang-Hei Chang

Tien-Chi Ke

A semiconductor device and a method of forming a semiconductor device include forming a dielectric material, performing a wet oxidation treatment on the dielectric material, and performing a dry anneal on the dielectric material. The dielectric material may be a flowable material. The wet oxidation treatment may include an acid and oxidizer mixture.

Semiconductor device and method of forming thereof

A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins over a substrate and embedded in isolation regions, depositing a first photoresist layer over the substrate, removing the first photoresist layer over an n-type region, applying a first ion implantation process to the first isolation regions, wherein dopants with a first polarity type are implanted in the first isolation regions, depositing a second photoresist layer over the substrate, removing the second photoresist layer over a p-type region, applying a second ion implantation process to the second isolation regions, wherein dopants with a second polarity type are implanted in the second isolation regions, applying an annealing process to the isolation regions and recessing the first isolation regions and the second isolation regions through an etching process.

FinFET structure with different fin heights and method for forming the same

To pattern a gate electrode, a mandrel of material is initially deposited and then patterned. In an embodiment the patterning is performed by performing a first etching process and to obtain a rough target and then to perform a second etching process with different etch parameters to obtain a precise target. The mandrel is then used to form spacers which can then be used to form masks to pattern the gate electrode.

Semiconductor methods and devices

Devices are described herein that include a first fin structure formed on a substrate. A second fin structure formed on the substrate. One or more gate structures are formed on the first fin structure and the second fin structure. A first in-fin source/drain region is associated with a first volume and is disposed between the first fin structure and the second fin structure. A fin-end source/drain region is associated with a second volume larger than the first volume, the first fin structure being disposed between the first in-fin source/drain region and the fin-end source/drain region. The gate structures, the first in-fin source/drain region, and the fin-end source/drain region are configured to form one or more transistors.

Structures and methods for fabricating semiconductor devices using fin structures

A FinFET and methods for forming a FinFET are disclosed. A method includes forming trenches in a semiconductor substrate to form a fin, depositing an insulating material within the trenches, and removing a portion of the insulating material to expose sidewalls of the fin. The method also includes recessing a portion of the exposed sidewalls of the fin to form multiple recessed surfaces on the exposed sidewalls of the fin, wherein adjacent recessed surfaces of the multiple recessed surfaces are separated by a lattice shift. The method also includes depositing a gate dielectric on the recessed portion of the sidewalls of the fin and depositing a gate electrode on the gate dielectric.

FinFETs and methods for forming the same

A shallow trench isolation (STI) structure is formed on a substrate. Part of the STI structure is removed to form a first fin structure and a second fin structure extending above a support structure on the substrate. A first part of the STI structure is located between the first fin structure and the second fin structure and has a first top surface higher than an interface between the first fin structure and the support structure. A second part of the STI structure is located adjacent to the first fin structure and has a second top surface lower than the interface between the first fin structure and the support structure. An etching process is performed to remove part of the first fin structure and the second fin structure. Part of the support structure adjacent to the second part of the STI structure is removed during the etching process.

A finFET and methods for forming a finFET are disclosed. A structure comprises a substrate, a fin, a gate dielectric, and a gate electrode. The substrate comprises the fin. The fin has a major surface portion of a sidewall, and the major surface portion comprises at least one lattice shift. The at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the sidewall. The gate electrode is on the gate dielectric.

A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins protruding over a substrate, wherein two adjacent first fins are separated from each other by a plurality of first isolation regions and two adjacent second fins are separated from each other by a plurality of second isolation regions. The method further comprises applying a first ion implantation process to the first isolation region, wherein dopants with a first polarity type are implanted in the first isolation region, applying a second ion implantation process to the second isolation region, wherein dopants with a second polarity type are implanted in the second isolation region and recessing the first isolation regions and the second isolation regions through an etching process.

A new processing sequence is provided for the process of creating salicided layers of CoSi . A conventional gate electrode is formed up to the point where the process of salicidation has to be performed. At that time a layer of cobalt is deposited over the surface of the gate electrode, a first anneal is applied to the deposited layer of cobalt. The layer of cobalt is then selectively etched to formed the contact surfaces of the gate electrode after which, significantly and as a major deviation from previous methods of creating a salicided layer of CoSi , silicon is implanted into the surface of the created layer of CoSi . This silicon implant relieves a silicon deficiency into the first annealed layer of CoSi , this silicon deficiency has experimentally been determined as being the essential cause for the occurrence of Co&mdash;Si agglomeration after a second thermal anneal. After the silicon implantation has been completed, a second thermal anneal is applied to the created layer of CoSi . The occurrence of Co&mdash;Si agglomeration is in this manner essentially eliminated.

Silicon implant in a salicided cobalt layer to reduce cobalt-silicon agglomeration

A method is taught for removing a silicon oxynitride ARC from over a polysilicon gate after the gate is patterned. The ARC is removed by wet etching without damaging or undercutting the polysilicon gate. This is accomplished by protecting the lateral sides of a polysilicon gate with a thin silicon oxide layer prior to the performing the wet etch. The method is primarily directed towards removal of a silicon oxynitride ARC layer from the upper surface of the polysilicon gate electrode in a salicide process, although a silicon nitride layer may also be removed by the same method. The protective silicon oxide is formed by rapid thermal oxidation in O or by plasma oxidation in O and H O. After oxidation, the ARC is removed with hot H PO . The protective silicon oxide protects the lateral surfaces of the polysilicon gate from attack by the acid. Following implantation of LDD regions, a conformal sidewall layer is deposited and the sidewalls formed in the conventional manner. When oxide/nitride sidewalls are formed, the protective oxide serves as a pad layer under the nitride. The method is particularly effective in preventing stress induced cracks in a composite oxide/nitride sidewall which has a foot. Elimination of gate undercutting by gate edge protection, according to the method described, eliminates excessive sidewall thickness in the vicinity of the corner at the foot and thereby minimizes stress in this region.

Method of silicon oxynitride ARC removal after gate etching

A method of forming a misalignment immune antifuse is presented comprised of the following steps. A partially processed semiconductor wafer is provided, containing at least one device electrically connected to a conducting region extending almost to the wafer surface, where the conducting region is surrounded by a dielectric layer which reaches the wafer surface. A blanket layer of amorphous silicon is deposited followed by deposition of a thin blanket layer of TiN and these layers are etched down to the dielectric surface except for that above the conducting region and some of the surrounding dielectric. A thin native oxide is formed over the exposed surface of the amorphous silicon. This is followed by deposition of a thicker TIN layer and of a metallization layer, which are patterned and etched so that contact is made to the lower layers. The oxidation step is repeated so as to oxidize any amorphous silicon surface that may have been inadvertently exposed in the last etching step.

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Taipei, Taiwan

Chi-Kang Liu