Advanced Micro Devices Corporation

Spansion Llc.

Other

Fujitsu Corporation

Cypress Semiconductor Corporation

Fasl LLC

Fujitsu Amd Semiconductor Limited

Chi K Chang

Yu Nan Sun

Sameer S Haddad

Mark T Ramsbey

Angela Tai Hui

Hiroyuki Kinoshita

Wei Zheng

Unsoon Kim

Tuan Duc Pham

Mark S Chang

Chungho Lee

Richard M Fastow

Michael Allen Van Buskirk

Mark W Randolph

Kuo-Tung Chang

Timothy J Thurgate

Narbeh Derhacobian

Vei-Han Chan

David K Liu

Yuan Tang

Fei Wang

Yue-Song He

Yider Wu

Hung-Sheng Chen

Tatsuya Kajita

Chung-You Hu

Zhigang Wang

Richard J Huang

Lee Edward Cleveland

Binh Quang Le

Shane Charles Hollmer

Daniel Sobek

Ming Sang Kwan

Michael Van Buskirk

Kyunghoon Min

Shoichi Kawamura

Mike Van Buskirk

Minh Van Ngo

Hidehiko Shiraiwa

Pau-Ling Chen

Jean Y Yang

Tazrien Kamal

Ashot Melik-Martirosian

Amol Ramesh Joshi

Chung K Chang

Joseph G Pawletko

James C Yu

Kelwin Ko

Sheunghee Park

Keizaburo Yoshie

Hiroyuki Ogawa

Shenqing Fang

Michael K Templeton

Hao Fang

Ning Cheng

Yi He

Ravi Prakash Gutala

Zhizheng Liu

Lei Xue

Meng Ding

Rinji Sugino

Wenmei Li

Satoshi Torii

Huaqiang Wu

Edward Franklin Runnion

Jihwan Choi

Fred Cheung

Jonathan S Su

Sheung-Hee Park

Janet S Y Wang

Fred T K Cheung

Robert Bertram Ogle, Jr

Paul S Baclit

Sheung Hee Park

K Michael Han

Paul-Ling Chen

Narbeth Derhacobian

Daniel Sobeck

Antonio Matalvo

Kuk S Yoon

Kevin W Plouse

Raymond Yu

Sugino Rinji

Ngaching Wong

Yu Sun

An embodiment of the present invention is directed to a memory cell. The memory cell includes a first trench formed in a semiconductor substrate and a second trench formed in said semiconductor substrate adjacent to said first trench. The first trench and the second trench each define a first side wall and a second sidewall respectively. The memory cell further includes a first storage element formed on the first sidewall of the first trench and a second storage element formed on the second sidewall of the second trench.

Flash memory cells having trenched storage elements

An embodiment of the present invention is directed to a memory cell. The memory cell includes a first charge storage element and a second charge storage element, wherein the first and second charge storage elements include nitrides. The memory cell further includes an insulating layer formed between the first and second charge storage elements. The insulating layer provides insulation between the first and second charge storage elements.

Dual storage node memory

Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes are disclosed. A disclosed method includes forming a first trench and an adjacent second trench in a semiconductor substrate, the first trench and the second trench each defining a first sidewall and a second sidewall respectively and forming a first source/drain region in the substrate and a second source/drain region in the substrate, where the first source/drain region and the second source/drain region are formed substantially under the first trench and the second trench in the semiconductor substrate respectively. Moreover, a method includes forming a bit line punch through barrier in the substrate between the first source/drain region and the second source drain region and forming a first storage element on the first sidewall of the first trench and a second storage element on the second sidewall of the second element. A word line is formed in contact with the first storage element and the second storage element.

Method for fabricating memory cells having split charge storage nodes

A memory cell system including providing a substrate, forming a charge-storing stack having silicon-rich nitride on the substrate, and forming a gate on the charge-storing stack.

Memory cell system using silicon-rich nitride

Methods of replacing/reforming a top oxide around a charge storage element of a memory cell and methods of improving quality of a top oxide around a charge storage element of a memory cell are provided. The method can involve removing a first poly over a first top oxide from the memory cell; removing the first top oxide from the memory cell; and forming a second top oxide around the charge storage element. The second top oxide can be formed by oxidizing a portion of the charge storage element or by forming a sacrificial layer over the charge storage element and oxidizing the sacrificial layer to a second top oxide.

Gate replacement with top oxide regrowth for the top oxide improvement

A dual node memory device and methods for fabricating the device are provided. In one embodiment the method comprises forming a layered structure with an insulator layer, a charge storage layer, a buffer layer, and a sacrificial layer on a semiconductor substrate. The layers are patterned to form two spaced apart stacks and an exposed substrate portion between the stacks. A gate insulator and a gate electrode are formed on the exposed substrate, and the sacrificial layer and buffer layer are removed. An additional insulator layer is deposited overlying the charge storage layer to form insulator-storage layer-insulator memory storage areas on each side of the gate electrode. Sidewall spacers are formed at the sidewalls of the gate electrode overlying the storage areas. Bit lines are formed in the substrate spaced apart from the gate electrode, and a word line is formed that contacts the gate electrode and the sidewall spacers.

Dual charge storage node memory device and methods for fabricating such device

A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

Semiconductor memory comprising dual charge storage nodes and methods for its fabrication

Dual storage node memory devices and methods for fabricating dual storage node memory devices have been provided. In accordance with an exemplary embodiment, a method includes the steps of etching a plurality of trenches in a semiconductor substrate and forming a layered structure within the trenches. The layered structure includes a tunnel dielectric layer and a charge storage layer. Bit lines are formed within the semiconductor substrate and a layer of conductive material is deposited overlying the layered structure.

Dual storage node memory devices and methods for fabricating the same

A device includes a substrate and multiple wells formed over the substrate and isolated from one another by dielectric trenches. The device further includes multiple memory elements formed over the wells, each of the memory elements extending approximately perpendicular to the wells and including a material doped with n-type impurities. The device also includes multiple source/drain regions, each source/drain region formed within one of multiple trenches and inside one of the plurality of wells between a pair of the memory elements, each of the source/drain regions implanted with p-type impurities. The device further includes a first substrate contact formed in a first one of the multiple trenches through a first one of the wells into the substrate and a second substrate contact formed in a second one of the multiple trenches through a second one of the wells into the substrate.

P-channel NAND in isolated N-well

A memory cell and a method of forming the same are described. The memory cell is formed on a substrate. The memory cell includes a floating gate that is formed at least in part within the substrate. A bit line region is formed within the substrate in proximity to the floating gate. Because of the configuration of the bit line and the floating gate, memory cells can be located closer to each other, increasing the density of memory cells in a memory array.

Flash memory with buried bit lines

A non-volatile memory device includes a semiconductor substrate and an N-type source and drain within the substrate. An oxide-nitride-oxide (ONO) stack is formed over the substrate. The ONO stack includes a thin bottom oxide layer. A Ppolysilicon gate electrode is formed over the ONO stack. The memory device is operative to perform a channel erase operation in which a pair of charge storing cells within the nitride layer are erased simultaneously.

Memory device having a P+ gate and thin bottom oxide and method of erasing same

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Houston, TX, United States of America

Chi K Chang