S3 Incorporated, Inc.

S3 Graphics Co., Ltd.

Chi-Jung Huang

Ken Ming Li

Ken-Ming Li

Helen Peng

On-chip resistance, capacitance and/or inductance is implemented in an integrated circuit in vertical configurations using stacked vias and medullization layers within the integrated circuit. Column shaped openings or vias are formed within the integrated circuit and connect from a silicon substrate to various metal traces. The vias are filled with conductive material such as platinum or tungsten. Parallel vias are used to form capacitance, while multiple vias and metal traces are arranged in various patterns over several planes in order to form resistance and/or inductance. The use of the stacked vias and metal traces in a vertical fashion reduces lateral spacing required to implement on-chip resistance, capacitance and/or inductance and allows for more efficient use of space in very large scale integration.

Method for implementing resistance, capacitance and/or inductance in an integrated circuit

A system and method for analyzing timing and noise effects in a hybrid circuit which contains a plurality of electrical components. The timing and noise effects for the hybrid circuit are generated by simulating electrical conditions within a hybrid circuit model. The hybrid circuit model is constructed by creating and integrating analog and behavioral models from the plurality of electrical components. The timing and noise effects remain accurate even at high printed circuit board/multi-chip module clock speeds, thereby ensuring that a user is able to construct an optimal design for any one of the plurality of electrical components.

Hybrid circuit model simulator for accurate timing and noise analysis

A graphics processing system incorporates a calibrator module into the system. As a memory module continuously transmits a model data signal, the calibrator module automatically increments the number of stages of delay, which are integrated into a delayed clock signal. Each delayed clock signal triggers the sampling of the model data signal by a plurality of latches. The calibrator module compares each of these sampled data signals with the original model data signals. If the delayed clock signal is properly aligned with the model data signal to cause the two signals to match, the calibrator module stores a result signal in a '1' logic state. If the delayed clock signal is misaligned with the model data signal, the calibrator module will store the result signal in a '0' logic state. When all of the possible stages of delay have been activated by the calibrator module and the corresponding sampled data signals analyzed, a processor module determines the optimum number of stages of delay needed for proper alignment of the delayed clock signal with the transmitted model data signal

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Saratoga, CA, United States of America

Chi-Jung Huang