Intel Corporation

Chi-Hwa Tsang

Shaestagir Chowdhury

Robert S Chau

Gilbert W Dewey

Willy Rachmady

Patrick R Morrow

Aaron D Lilak

Hui Jae Yoo

Kimin Jun

Christopher J Jezewski

Anh Phan

Tristan A Tronic

Jessica M Torres

Charles Henry Wallace

Manish Chandhok

Florian Gstrein

Rami Hourani

Paul Anton Nyhus

Ruth Amy Brain

Eungnak Han

Sean W King

Leopoldo D Yau

Vinay B Chikarmane

Daniel J Zierath

Peter K Charvat

Kerry L Spurgin

Galen H Kawamoto

William L Hargrove

Hossein Rojhantalab

Robert M Guptill

Deborah A Parsons

Ganesan Radhakrishnan

A stacked device structure includes a first device structure including a first body that includes a semiconductor material, and a plurality of terminals coupled with the first body. The stacked device structure further includes an insulator between the first device structure and a second device structure. The second device structure includes a second body such as a fin structure directly above the insulator. The second device structure further includes a gate coupled to the fin structure, a spacer including a dielectric material adjacent to the gate, and an epitaxial structure adjacent to a sidewall of the fin structure and between the spacer and the insulator. A metallization structure is coupled to a sidewall surface of the epitaxial structure, and further coupled with one of the terminals of the first device.

Metallization structures for stacked device connectivity and their methods of fabrication

Conductive cap-based approaches for conductive via fabrication is described. In an example, an integrated circuit structure includes a plurality of conductive lines in an ILD layer above a substrate. Each of the conductive lines is recessed relative to an uppermost surface of the ILD layer. A plurality of conductive caps is on corresponding ones of the plurality of conductive lines, in recess regions above each of the plurality of conductive lines. A hardmask layer is on the plurality of conductive caps and on the uppermost surface of the ILD layer. The hardmask layer includes a first hardmask component on and aligned with the plurality of conductive caps, and a second hardmask component on an aligned with regions of the uppermost surface of the ILD layer. A conductive via is in an opening in the hardmask layer and on a conductive cap of one of the plurality of conductive lines.

Conductive cap-based approaches for conductive via fabrication and structures resulting therefrom

Techniques are disclosed that enable interconnects, vias, metal gates, and other conductive features that can be formed through electroless material deposition techniques. In some embodiments, the techniques employ electroless fill in conjunction with high growth rate selectivity between an electroless nucleation material (ENM) and electroless suppression material (ESM) to generate bottom-up or otherwise desired fill pattern of such features. Suitable ENM may be present in the underlying or otherwise existing structure, or may be provided. The ESM is provisioned so as to prevent or otherwise inhibit nucleation at the ESM covered areas of the feature, which in turn prevents or otherwise slows down the rate of electroless growth on those areas. As such, the electroless growth rate on the ENM sites is higher than the electroless growth rate on the ESM sites.

Electroless filled conductive structures

Methods of fabricating an interconnect utilizing an electroless deposition technique, which fundamentally comprises providing a dielectric material layer having an opening extending into the dielectric material from a first surface thereof, and electrolessly depositing a conductive material within the opening. A dual-function barrier layer is formed within the opening. The dual-function barrier layer is capable of acting as a diffusion barrier layer and a nucleation surface for a conductive material. An electrolessly deposited conductive material is formed immediately above the dual-function barrier layer. An ultra-thin seed layer may be formed immediately on top of the barrier layer prior to the electrolessly deposited conductive material being formed thereon.

Filling narrow and high aspect ratio openings with electroless deposition

Methods of fabricating an interconnect utilizing an electroless deposition technique, which fundamentally consists of providing a dielectric material layer having an opening extending into the dielectric material from a first surface thereof, and electrolessly depositing a conductive material within the opening. Various processing steps and structures may be utilized in the fabrication of the interconnect, which may include but is not limited to forming barrier layers, utilizing seed materials, utilizing activation materials, and treating the dielectric material to be receptive to electroless deposition.

Filling narrow and high aspect ratio openings using electroless deposition

Apparatus and method for treating a surface of a substrate for electrolytic or electroless plating of metals in integrated circuit manufacturing. In one embodiment the method includes forming a barrier layer on a substrate. A metal-seed layer is then formed on the barrier layer. The method continues by performing in situ surface treatment of the metal-seed layer to form a passivation layer on the metal-seed layer. In another embodiment of a method of this invention, a substrate is provided into an electroplating tool chamber. The substrate has a barrier layer formed thereon, a metal seed layer formed on the barrier layer and a passivation layer formed over the metal seed layer. The method continues by annealing the substrate in forming gas to reduce the passivation layer. A conductive material is deposited on the substrate using an electrolytic plating or electroless plating process.

Apparatus and method of surface treatment for electrolytic and electroless plating of metals in integrated circuit manufacturing

A method and system for reclaiming virgin test wafers by polishing a very thin layer from the wafer surface, applying a low down force between the wafer and the pad, with a dilute, low basic slurry. By polishing only a few hundred Angstroms of silicon from the wafer surface, a virgin test wafer may be repeatedly reclaimed and reused for periodic defect monitoring.

Reclaiming virgin test wafers

A method of forming and refilling a trench in a substrate. First a trench is formed in the substrate. The trench is then refilled with a conformal material. Next, a recess is etched into the top portion of the refilled trench. The recess is then refilled with a second material until the refilled recess and substrate are substantially planar.

Trench isolation with planar topography and method of fabrication

A dry process for stripping photoresist from a polyimide surface formed on a substrate is described. The present invention is practiced after a polyimide layer has been etched. Prior to etching, the polyimide surface is masked with photoresist which is then patterned. The polyimide is etched in exposed regions, for example to form vias to expose contacts located beneath the polyimide layer. The present invention then strips the photoresist in a single wafer downstream plasma etcher in a plasma comprising oxygen radicals. The polyimide is subjected to a short preheat before introduction of the oxygen plasma, and is also heated during the stripping process. The strip proceeds until an endpoint is detected. The endpoint is detected by a change in the spectral emission of the plasma which occurs due to a decrease in the amount of CH.sub.3 radicals present in the system when the polyimide surface is reached. A short timed over-etch is then employed to ensure complete removal of the photoresist. The stripping process of the present invention selectively strips photoresist compared to polyimide, so that exposed portions of the polyimide surface are not significantly etched during the timed overetch.

Dry process for stripping photoresist from a polyimide surface

An anisotropic plasma etching of a tungsten metal film of a semiconductor device is disclosed. The device is placed in a plasma etcher using SF.sub.6 and Cl.sub.2 gas mixture to anisotropically etch the tungsten metal film layer.

Anisotropic plasma etching of tungsten

A process for delineating a vertical resistor on a semiconductor device is disclosed. Resistive and diffusion barrier layers are deposited and then etched, first by dry plasma and then by wet bath. The two step etching allows complete removal of the deposited layers with minimal damage to exposed dielectric, silicide, polysilicon or doped regions on the semiconductor.

Pattern delineation of vertical load resistor

A method of plasma etching silicon using a fluorinated gas mixture. A mixture of CHF3 and SF6 is utilized in an etch chamber to form a plasma for etching silicon. The degree of anisotropy of the etch can be controlled by changing the percentage of CHF3 in the CHF3/SF6 mixture. The method does not adversely affect the etched surface so that no post-etch thermal process step is required to cure the silicon surface.

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Beaverton, OR, United States of America

Chi-Hwa Tsang