Taiwan Semiconductor Manufacturing Comp. Ltd.

Chi-Hsun Hsieh

Bao-Ru Young

Wei Cheng Wu

Harry Hak-Lay Chuang

Po-Nien Chen

Eric Huang

Hsun-Ying Huang

Yi-Ming Sheu

Yung-Cheng Chang

Amey Mahadev Walke

Yu-Hsuan Kuo

Jia-Ren Chen

Shou Shu Lu

Yung-Fu Yeh

Juan-Lin Chen

Che-Min Chu

Cheng-Tsung Chen

Yu-Ping Chen

Chi-Yuan Liang

Horng-Daw Shen

Syun-Ming Jang Jang

Da-Wen Lin

Yo-Sheng Lin

Chu-Yun Fu

Chih-Heng Shen

Ching-Chen Hao

Chao-Chi Chen

An exemplary integrated circuit comprises: a first device gate disposed over the first device region, the first device gate comprising a first interfacial layer and a first dielectric layer; a second device gate disposed over the second device region, the second device gate comprising a second interfacial layer and a second dielectric layer; and a third device gate disposed over the third device region, the third device gate comprising a third interfacial layer and a third dielectric layer, wherein the first interfacial layer, the second interfacial layer, and the third interfacial layer are different from each other in at least one of a thickness and an interfacial material.

Circuit incorporating multiple gate stack compositions

The present disclosure provides an FET structure including a transistor of a first conductive type. The transistor includes a substrate having a region of a second conductive type, a channel between source and drain, and a gate over the channel. The channel includes dopants of the first conductive type. The gate includes a work function setting layer of the second conductive type. The present disclosure also provides a method for manufacturing an FET with multi-threshold voltages scheme. The method includes exposing channels of a first transistor of a first conductive type and a first transistor of a second conductive type from a first mask, doping the channels with dopants of the first conductive type, exposing channels of a second transistor of the first conductive type and a second conductive type from a second mask, and doping the channels with dopants of the second conductive type.

Multi-threshold voltage field effect transistor and manufacturing method thereof

A method including providing a substrate having a first region, a second region, and a third region defined thereupon. A first interfacial layer is formed over the first region, the second region, and the third region. The first interfacial layer is etched to remove a portion of the first interfacial layer from the first region and a portion of the first interfacial layer from the second region. Etching of the first interfacial layer defines a gate stack within the third region. After the etching of the first interfacial layer, a second interfacial layer is formed over at least a portion of the second region. The second interfacial layer is etched to define a gate stack within the second region. After the etching of the second interfacial layer, a third interfacial layer is formed on the substrate over at least a portion of the first region to define a gate stack within the first region.

Methods of fabricating multiple gate stack compositions

An integrated circuit having multiple different device gate configurations and a method for fabricating the circuit are disclosed. An exemplary embodiment of forming the circuit includes receiving a substrate having a first device region, a second device region, and a third device region. A first interfacial layer is formed over at least a portion of each of the first device region, the second device region, and the third device region. The first interfacial layer is patterned to define a gate stack within the third device region. A second interfacial layer is formed over at least a portion of the second device region. The second interfacial layer is patterned to define a gate stack within the second device region. A third interfacial layer is formed over at least a portion of the first device region. The third interfacial layer defines a gate stack within the first device region.

Method of fabricating multiple gate stack compositions

A system and method for image sensing is disclosed. An embodiment comprises a substrate with a pixel region, the substrate having a front side and a backside. A co-implant process is performed along the backside of the substrate opposing a photosensitive element positioned along the front side of the substrate. The co-implant process utilizes a first pre-amorphization implant process that creates a pre-amorphization region. A dopant is then implanted wherein the pre-amorphization region retards or reduces the diffusion or tailing of the dopants into the photosensitive region. An anti-reflective layer, a color filter, and a microlens may also be formed over the co-implant region.

Co-implant for backside illumination sensor

A method is provided for improving Idsat in NMOS and PMOS transistors. A silicon nitride etch stop layer is deposited by a PECVD technique on STI and silicide regions and on sidewall spacers during a MOSFET manufacturing scheme. A dielectric layer is formed on the nitride and then contact holes are fabricated through the dielectric layer and nitride layer to silicide regions and are filled with a metal. For NMOS transistors, silane and NHflow rates and a 400&#xb0; C. temperature are critical in improving NMOS short channel Idsat. Hydrogen content in the nitride is increased by higher NHand SiHflow rates but does not significantly degrade HCE and Vt. With PMOS transistors, deposition temperature is increased to 550&#xb0; C. to reduce hydrogen content and improve HCE and Vt stability.

N/PMOS saturation current, HCE, and Vt stability by contact etch stop film modifications

A thermal oxidation method for forming a gate dielectric layer for use within a field effect transistor device employs a thermal oxidizing atmosphere comprising a halogen getter material. By employing the halogen getter material, the field effect transistor device is formed with enhanced performance, in particular with respect to negative bias temperature instability lifetime.

Halogen gettering method for forming field effect transistor (FET) device

Within a method for fabricating a semiconductor integrated circuit microelectronic fabrication, there is employed a planarizing method for forming, in a self aligned fashion, a patterned second gate electrode material layer laterally adjacent but not over a patterned first gate electrode material layer, such that upon further patterning of the patterned first gate electrode material layer and the patterned second gate electrode material layer there may be formed a first gate electrode over a first active region of a semiconductor substrate and a second gate electrode over a laterally adjacent second active region of the semiconductor substrate. The method is particularly useful within the context of complementary metal oxide semiconductor (CMOS) semiconductor integrated circuit microelectronic fabrications.

Planarizing method for fabricating gate electrodes

Growing community of inventors

Taichung, Taiwan

Chi-Hsun Hsieh