Winbond Electronics Corporation

Windbond Electronics Corp.

Chi-Hsiang Sun

Zong-Ying Ho

Shih-Nung Wei

Joonho Kim

A delay locked loop includes a delay line, a phase detector, a controller, an output clock generator, and a feedback circuit. The delay line receives an input clock signal and a control code, and generates a delayed clock signal by delaying the input clock signal according to the control code. The phase detector receives a reference clock signal and a feedback clock signal, and detects a phase difference between the reference clock signal and the feedback clock signal to generate phase comparison information. The controller generates the control code and a switching signal according to the phase comparison information. The output clock generator selects the delayed clock signal or an inverted signal of the delayed clock signal according to the switching signal to generate an output clock signal. The feedback circuit generates the feedback clock signal according to the output clock signal.

Delay locked loop

A control circuit of delay lock loop and a control method thereof are provided. The control circuit includes a power status detector, a voltage comparator, an enable signal generator and a control signal generator. The power status detector detects a transition edge of a clock enable signal to generate a trigger signal corresponding to a variation of an operation power. The voltage comparator compares the operation power with a reference voltage to generate a comparison result. The enable signal generator sets an enable signal to an active state according to the trigger signal and sets the enable signal to a non-active state according to the comparison result. The control signal generator outputs a control clock to generate a control signal when the enable signal is in the active state.

Control circuit of delay lock loop and control method thereof

A delay lock loop and a phase locking method thereof are provided. The delay lock loop includes a first divider, a delay line, a frequency multiplier, a second divider, a phase detection and controlling circuit and a setting signal generator. The first divider generates a divided reference clock signal. The second divider generates a first feedback clock signal and a second feedback clock signal which are complementary by dividing an output clock signal, and generates a selected feedback clock signal by selecting the first or second feedback clock signal according to a setting signal. The phase detection and controlling circuit compares phases of the selected feedback clock signal and the divided reference clock signal to generate a delay control signal. The setting signal generator samples the divided reference clock signal by the first feedback clock signal to generate the setting signal.

Delay lock loop and phase locking method thereof

A delay-locked loop circuit and a selection method of unit coarse delay are provided. The delay-locked loop circuit includes a frequency detector and a unit coarse delay selector. The frequency detector receives a reset signal and a clock signal. The frequency detector performs a sampling operation to detect a clock frequency of the clock signal based on a time shift of the reset signal and a sequential delay of the reset signal to generate a plurality of determining signals. The unit coarse delay selector selects one of the plurality of determining signals with an earliest transition time as a selected coarse delay signal to control a timing of the delay-locked loop circuit.

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Taichung, Taiwan

Chi-Hsiang Sun