United Microelectronics Corp.

Chi-Horn Pai

Shih-Chieh Hsu

Sheng-Yuan Hsueh

Kuo-Hsing Lee

Chih-Kai Kang

Ying-Hung Chou

Chun-Hsien Lin

Jie-Ning Yang

Yao-Chang Wang

Zen-Jay Tsai

Chi-Sheng Tseng

Chang-Chien Wong

Ching-Hsiang Tseng

Yi-Chung Sheng

Shui-Yen Lu

Chia-Chen Sun

Po-Kuang Hsieh

Shao-Hua Hsu

Chun-Chia Chen

Shu-Hsuan Chih

Shih-Hao Su

Chieh-Te Chen

Kun-Hsien Lee

Po-Cheng Huang

Wen-Kai Lin

Chiu-Hsien Yeh

Shin-Chi Chen

Chien-Liang Wu

Po-Jui Liao

Tsung-Hsun Wu

Chih-Chung Chen

Kun-Szu Tseng

Te-Wei Yeh

Hung-Yi Wu

Tsung-Wen Chen

Huang-Yi Lin

Kuang-Hung Huang

Yung-Chen Chiu

Shih-Chang Chang

Chih-Ho Wang

Ching-Fang Chu

Jiun-Hung Shen

Guang-Wei Ye

Chang Chien Wong

Ching Hsiang Tseng

The present disclosure provides, the semiconductor device includes a substrate, a first transistor, a capacitor, and two first plugs. The substrate has a high-voltage region and a capacitor region. The first transistor is disposed in the high-voltage region, and includes a first gate dielectric layer, a first gate electrode, and a first capping layer. The capacitor is disposed in the capacitor region and includes a second gate electrode, a second capping layer, a dielectric layer, and a conductive layer. The two first plugs are disposed on the capacitor, wherein one of the two first plugs penetrates through the second capping layer to directly contact the second gate electrode, and another one of the two first plugs directly contacts the conductive layer.

Semiconductor device and method of fabricating the same

A one-time programmable (OTP) memory cell includes a substrate having an active area surrounded by an isolation region. A divot is disposed between the active area and the isolation region. A transistor is disposed on the active area. A diffusion-contact fuse is electrically coupled to the transistor. The diffusion-contact fuse includes a diffusion region in the active area, a silicide layer on the diffusion region, and a contact partially landed on the silicide layer and partially landed on the isolation region. A sidewall surface of the diffusion region in the divot is covered by the silicide layer. The divot is filled with the contact.

One-time programmable memory cell

A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first NMOS region, a first PMOS region, a second NMOS region, a second PMOS region, and a MOS capacitor region, forming a fin NMOS transistor on the first NMOS region, forming a fin PMOS transistor on the first PMOS region, forming a planar NMOS transistor on the second NMOS region, forming a planar PMOS transistor on the second PMOS region, and forming a planar MOS capacitor on the MOS capacitor region.

Semiconductor device and method for fabricating the same

A bit cell structure for one-time programming is provided in the present invention, including a substrate, a first doped region in the substrate and electrically connecting a source line, a second doped region in the substrate and having a source and a drain electrically connecting a bit line, a heavily-doped channel in the substrate and connecting the first doped region and the source of second doped region, and a word line crossing over the second dope region between the source and the drain.

Bit cell structure for one-time-programming

A semiconductor memory structure includes a substrate having thereon a transistor forming region and a capacitor forming region. A transistor is disposed on the substrate within the transistor forming region. A capacitor is disposed within the capacitor forming region and electrically coupled to the transistor. A first inter-layer dielectric layer covers the transistor forming region and the capacitor forming region. The first inter-layer dielectric layer surrounds a metal gate of the transistor and a bottom plate of the capacitor. A cap layer is disposed on the first inter-layer dielectric layer. The cap layer has a first thickness within the transistor forming region and a second thickness within the capacitor forming region. The first thickness is greater than the second thickness. The cap layer within the capacitor forming region acts as a capacitor dielectric layer of the capacitor.

Semiconductor memory structure and fabrication method thereof

A one-time programmable memory structure including a substrate, a transistor, a capacitor, and an interconnect structure is provided. The transistor is located on the substrate. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is disposed above the substrate. The second electrode is disposed on the first electrode. The first electrode is located between the second electrode and the substrate. The insulating layer is disposed between the first electrode and the second electrode. The interconnect structure is electrically connected between the transistor and the first electrode of the capacitor. The interconnect structure is electrically connected to the first electrode at a top surface of the first electrode.

One-time programmable memory structure

A one-time programmable (OTP) memory cell includes a substrate comprising an active area surrounded by an isolation region, a transistor disposed on the active area, and a diffusion-contact fuse electrically coupled to the transistor. The diffusion-contact fuse includes a diffusion region in the active area, a silicide layer on the diffusion region, and a contact partially landed on the silicide layer and partially landed on the isolation region.

One-time programmable memory cell and fabrication method thereof

The invention provides a semiconductor memory cell, the semiconductor memory cell includes a substrate having a first conductivity type, a doped region in the substrate, wherein the doped region has a second conductivity type, and the first conductivity type is complementary to the second conductivity type, a capacitor insulating layer and an upper electrode on the doped region, a transistor on the substrate, and a shallow trench isolation disposed between the transistor and the capacitor insulating layer, and the shallow trench isolation is disposed in the doped region.

Semiconductor memory cell and the forming method thereof

The present invention provides a structure of a resistor comprising: a substrate having an interfacial layer thereon; a resistor trench formed in the interfacial layer; at least a work function metal layer covering the surface of the resistor trench; at least two metal bulks located at two ends of the resistor trench and adjacent to the work function metal layer; and a filler formed between the two metal bulks inside the resistor trench, wherein the metal bulks are direct in contact with the filler.

Resistor and fabrication method thereof

A method for forming a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, forming a transistor having a polysilicon dummy gate in the transistor region and a polysilicon main portion with two doped regions positioned at two opposite ends in the resistor region, performing an etching process to remove the polysilicon dummy gate to form a first trench and remove portions of the doped regions to form two second trenches, and forming a metal gate in the first trench to form a transistor having the metal gate and metal structures respectively in the second trenches to form a resistor.

Resistor and manufacturing method thereof

A test key structure for use in measuring step height includes a substrate, and a pair of test contacts. The substrate includes an isolation region and a diffusion region. The test contact pair includes a first test contact and a second test contact for measuring electrical resistances. The first test contact is disposed on the diffusion region and the second test contact is disposed on the isolation region.

Test key structure and method for measuring step height by such test key structure

A method for fabricating a semiconductor device is described. A gate layer, a C-doped first protective layer and a hard mask layer are formed on a substrate and then patterned to form a first stack in a first area and a second stack in a second area. A second protective layer is formed on the sidewalls of the first and the second stacks. A blocking layer is formed in the first area and a first spacer formed on the sidewall of the second protective layers on the sidewall of the second stack in the second area. A semiconductor compound is formed in the substrate beside the first spacer. The blocking layer and the first spacer are removed. The hard mask layer in the first stack and the second stack is removed.

Method for fabricating semiconductor device and PMOS device fabricated by the method

A semiconductor process is provided. The prior steps include: a first gate including a first cap layer and a second gate including a second cap layer are formed on a substrate. A hard mask layer is formed to cover the first gate and the second gate. The material of the hard mask layer is different from the material of the first cap layer and the second cap layer. The hard mask layer is removed entirely after a lithography process and an etching process are performed. The following steps include: a material is formed to entirely cover the first gate and the second gate. The material, the first gate and the second gate are etched back to make the first gate and the second gate have the same level and expose layers in both of them.

Semiconductor process

A manufacturing method for a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, respectively forming a transistor having a dummy gate in the transistor region and a resistor in the resistor region, removing the dummy gate and portions of the resistor to form a first trench in the transistor and two second trenches in the resistor, forming at least a high-k gate dielectric layer in the first trench and the second trenches, and forming a metal gate in the first trench and metal structures respectively in the second trenches.

A method of manufacturing a CMOS device includes providing a substrate having a first region and a second region; forming a first gate structure and a second gate structure, each of the gate structures comprising a sacrificial layer and a hard mask layer; forming a patterned first protecting layer covering the first region and a first spacer on sidewalls of the second gate structure; performing an etching process to form first recesses in the substrate; performing a SEG process to form epitaxial silicon layers in each first recess; forming a patterned second protecting layer covering the second region; and performing a dry etching process with the patterned second protecting layer serving as an etching mask to etch back the patterned first protecting layer to form a second spacer on sidewalls of the first gate structure and to thin down the hard mask layer on the first gate structure.

Method of manufacturing complementary metal oxide semiconductor device

Growing community of inventors

Tainan, Taiwan

Chi-Horn Pai