Nexperia B.v.

Nxp B.v.

X.on Communications Limited

Chi Ho Leung

Pompeo V Umali

Shun Tik Yeung

Kan Wae Lam

Chi Ling Shum

Soenke Habenicht

Hans-Juergen Funke

Wai Hung William Hor

Tim Boettcher

Wolfgang Schnitt

Zhihao Pan

Sven Walczyk

Wai Wong Chow

Haibo Fan

Harrie Martinus Maria Horstink

Yuet Fong

Ke Xue

San Ming Chan

Wai Keung Ng

WaiKeung Ho

Yee Wai Fung

Thierry Jans

Shu-Ming Yip

Wai (Kan Wae) Lam

An electronic device including a die and at least one lead. The electronic device further includes a corresponding at least one connector, each connector for connecting the die to a corresponding lead or leads, and each connector having a first end disposed in bondable proximity to a complementary surface of the corresponding lead and a second end disposed in bondable proximity to a complementary surface of the die. An end portion of at least one of the first end and second end has a formation, the formation in combination with the complementary surface of one, or both, of the respective lead or the die defining therebetween a first region and at least a second region configured to attract by capillary action an electrically conductive bonding material to consolidate therein.

Electronic device

A semiconductor device and a method of making the same. The device includes an electrically conductive heat sink having a first surface. The device also includes a semiconductor substrate. The device further includes a first contact located on a first surface of the substrate. The device also includes a second contact located on a second surface of the substrate. The first surface of the substrate is mounted on the first surface of the heat sink for electrical and thermal conduction between the heat sink and the substrate via the first contact. The second surface of the substrate is mountable on a surface of a carrier.

Semiconductor device

A semiconductor device includes a semiconductor die having a top surface that has one or more electrical contacts formed thereon, and an opposite bottom surface. A molding material encapsulates the top surface and at least a part of a side surface of the semiconductor die. The molding material defines a package body that has a top surface and a side surface. Openings are formed on the top surface of the package body, and the electrical contacts are partially exposed from the molding material through the openings. A metal layer is formed over and electrically connected to the electrical contacts through the openings. The metal layer extends to and at least partially covers the side surface of the package body.

Wafer level semiconductor device with wettable flanks

An electronic device has a first surface, a second surface opposite to the first surface, and sidewalls located between and adjoining the first and second surfaces. The electronic device includes contact pads on the first surface. The contact pads extend from the first surface to adjoining sidewalls, and abut the sidewalls.

Electronic device and method of making same

A semiconductor die has internal circuitry formed on two more internal layers, and die bonding pads arranged on a top surface of the die. The bonding pads are connected to the internal circuitry for providing input and output signals to the internal circuitry. One or more connecting lines electrically connect one or more pairs of the die bonding pads, thereby defining a bonding pad layout. The die bonding pads are arranged and connected with the connecting lines such that the bonding pad layout is reversible, which allows the die to be used in different package types (e.g., TSSOP or DFN) yet maintain a standardized pin arrangement without the necessity for long or crossed bond wires.

Reversible semiconductor die

A semiconductor device includes a semiconductor die having a first side having a first terminal and an opposite second side having at least two second terminals. A lead frame has a first part and a second part. The second part of the lead frame is both electrically and mechanically spaced from the first part. The second side of the die is attached to the lead frame such that the first and second lead frame parts are respectively connected to the at least two second terminals. The first and second lead frame parts include respective first and second extensions that project past a side of the die and provide first and second terminal surfaces that are co-planar with the first terminal on the first side of the die. The device makes use of the terminals on the both sides of the die. The device second side is exposed for thermal performance.

Semiconductor device and lead frame therefor

A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, one or more contacts located on the major surface and an encapsulant covering at least the major surface. A peripheral edge of each contact defines a contact area on the major surface. The device also includes one or more bond pads located outside the encapsulant. Each bond pad is electrically connected to a respective contact located on the major surface of the substrate by a respective metal filled via that passes through the encapsulant. A sidewall of each respective metal filled via, at the point at which it meets the respective contact, falls inside the contact area defined by the respective contact when viewed from above the major surface of the substrate, whereby none of the metal filling each respective via extends outside the contact area of each respective contact.

Semiconductor device and method of making a semiconductor device

Consistent with an example embodiment, a semiconductor device comprises a device die having bond pads providing connection to device die circuitry. The semiconductor device includes a built-up substrate lead frame having, a sub-structure of I/O terminals and a die attach area, the I/O terminals and die attach area enveloped in a molding compound, the die attach area having exposed areas to facilitate device die attachment thereon and the terminal I/O terminals providing connection to the device die bond pads; connection traces electrically couple the I/O terminals with one another, said connection traces having facilitated electroplating of exposed vertical surfaces of the I/O terminals during assembly, said connection traces being severed after assembly. An envelope of molding compound encapsulates the device die onto the built-up substrate lead frame.

Built-up lead frame package and method of making thereof

The present invention relates to a wireless communication system and a method thereof. The wireless communication system comprises a signal encoding module for encoding a preset high-frequency audio signal frequency according to a preset encoding rule, and creating an encoding library for storing the code; a signal sampling module for sampling a high-frequency audio signal produced by a high-frequency audio signal generating device; a signal transformation module for performing Fourier transformation on the sampled audio signal firstly to transform the audio signal into frequencies, acquiring a main frequency from the transformed frequencies, and storing the acquired main frequency; a signal decoding module for decoding the main frequency into a preset code according to the code in the library; and an output module for outputting the decoded code. The wireless communication system and the method of the present invention do not need hardware supports, thereby reducing the cost.

Wireless communication system and method thereof

A method of forming semiconductor devices on a leadframe structure. The leadframe structure comprising an array of leadframe sub-structures each having a semiconductor die arranged thereon. The method comprises; providing electrical connections between terminals of said lead frame sub-structures and said leadframe structure; encapsulating said leadframe structure, said electrical connections and said terminals in an encapsulation layer; performing a first series of parallel cuts extending through the leadframe structure and the encapsulation layer to expose a side portion of said terminals; electro-plating said terminals to form metal side pads; and performing a second series of parallel cuts angled with respect to the first series of parallel cuts, the second series of cuts extending through the lead frame structure and the encapsulation layer to singulate a semiconductor device from the leadframe structure.

Leadless semiconductor package and method

Consistent with an example embodiment, there is leadless packaged semiconductor device having top and bottom opposing major surfaces and sidewalls extending there between. The leadless packaged semiconductor device comprises a lead frame sub-assembly having an array of two or more lead frame portions each having a semiconductor die arranged thereon. There are at least five I/O terminals wherein each of said terminals comprise a respective metal side pad wherein the respective metal side pad is disposed in a recess. A feature of this embodiment is that the each of the side pads is electroplated. The electroplated side pads accept solder and the solder menisci are contained by the recesses.

Package with multiple I/O side-solderable terminals

Consistent with an example embodiment, a semiconductor device comprises a device die having bond pads providing connection to device die circuitry. The semiconductor device includes a QFN package (quad-flat-pack no-leads) built-up substrate lead frame having, a sub-structure of I/O terminals and a die attach area, the I/O terminals and die attach area enveloped in a molding compound; the die attach area has exposed areas to facilitate device die attachment thereon and the terminal I/O terminals provide connection to the device die bond pads. I/O terminals are electrically coupled with one another and to the die attach area with connection traces. The coupled I/O terminals and connection traces facilitate electroplating of exposed vertical surfaces of the I/O terminals during assembly, said connection traces being severed after assembly. Molding compound encapsulates the device die on the built-up substrate lead frame. The exposed vertical surfaces of the I/O terminals enhance the solderability of the assembled QFN device during placement onto a printed circuit board.

Growing community of inventors

Hong Kong, China

Chi Ho Leung