Marvell International Limited

Other

Actel Corporation, Inc.

Microsemi Soc Corporation

Chi Fung Cheng

Pantas Sutardja

Akimi C Cheng

Sinan Kaptanoglu

King W Chan

William C T Shu

Hongxin Song

Arshan Aga

Steve Fang

Mickie H Cheng

Michael W Cheng

A system includes an ADC that, based on a first clock signal, converts an analog signal into a digital signal. A first circuit generates a second clock signal based on the digital signal. An interpolator generates a phase delayed version of the second clock signal and a third clock signal. The third clock signal is generated based on the second clock signal and the phase delayed version and includes transitioning from the second clock signal to the phase delayed version. The third clock signal includes pulses each having a first pulse width and a pulse having a second pulse width. The second pulse width is different than the first pulse width due to the transition from the second clock signal to the third clock signal. A second circuit removes the pulse having the second pulse width from the third clock signal to generate the first clock signal.

Method and system for removing a pulse having a different pulse width relative to that of other pulses in a clock signal of an analog to digital converter

An interface design for a hybrid IC that utilizes dedicated interface tracks to allow signals to interface distributively with the logic blocks of the FPGA portion providing for faster and more efficient communication between the FPGA and ASIC portions of the hybrid IC.

Dedicated interface architecture for a hybrid integrated circuit

According to an aspect of the present disclosure, a method includes: receiving a plurality of groups of one or more phase signals, each group of phase signals having a different phase relative to other groups of one or more phase signals; generating a plurality of interpolated phase shifted signals based on the plurality of groups of one or more phase signals, wherein the plurality of interpolated phase shifted signals do not have an associated common mode component; receiving data bits and precompensating each data bit in accordance with a given interpolated phase shifted signal; and selecting a precompensated data bit for output.

Method and system for precompensation of data output

The present disclosure includes systems and techniques relating to non-volatile memory. A described technique includes monitoring read-back data from a group of memory cells that are programmable based on a group of programming voltages, each of the memory cells being configured to represent two or more bits by a single charge level, the two or more bits corresponding to two or more bit positions; determining estimated mean and standard deviation values of level distributions of the memory cells based on the read-back data; and adjusting one or more of the programming voltages based on the estimated mean and standard deviations of the level distribution such that differences among bit error rates of the bit positions are reduced.

Non-volatile memory devices having uniform error distributions among pages

A data channel circuit including an analog to digital converter, a timing loop control circuit, an interpolator circuit, and a deglitch circuit. The analog to digital converter is configured to convert an analog input signal into a corresponding digital signal in accordance with a reference clock signal received from a timing loop. The timing loop control circuit is configured to receive the digital signal from the analog to digital converter, and generate a first clock signal based on the digital signal. The interpolator circuit is configured to receive the first clock signal, and generate a second clock signal based on the first clock signal, and the first clock signal delayed by a predetermined phase delay. The second clock signal has first glitches. The deglitch circuit is configured to, based on the second clock signal, generate the reference clock signal. The reference clock signal does not include the first glitches.

Data channel circuit with reference clock signal free of glitches

A device is provided that, in one implementation, includes interpolators to generate interpolated phase shifted signals, and a precompensation circuit to provide precompensated versions of data bits in accordance with the interpolated phase shifted signals. Each of the interpolators is assigned a bit pattern different from that assigned to remaining ones of the interpolators.

Method and apparatus for write precompensation in a magnetic recording system

An apparatus, method, and system for removing glitches from a clock signal, including a duty cycle lock loop (DCLL) circuit. A glitch, which may produce errors in the clock signal, may occur when a read channel transitions from an acquired clock signal to an adjusted clock signal. In one embodiment of the inventive deglitch circuit, a first capacitor is charged and discharged in response to an input clock signal, and an output clock signal is provided depending upon the first capacitor's voltage. The output clock signal further charges and discharges a second capacitor whose ratio of charge to discharge currents provides a signal to bias the discharge current of the first capacitor. A second DCLL circuit may be provided to restore the output clock signal duty cycle to the original clock signal duty cycle.

Deglitch circuit removing glitches from input clock signal

A phase locked loop (PLL) is provided. In one implementation, the PLL includes a multiphase voltage controlled oscillator (VCO) operable to generate an output signal containing one or more phase signals, a programmable divider operable to divide a frequency of the output signal of the multiphase VCO to produce a divided frequency output signal, and a fractional divider to fractionally divide an input phase signal. The fractional divider can include an integer divider operable to receive the input phase signal and divide the input phase signal in accordance with an integer divisor to produce a divided signal as an input to the multiphase VCO, and a phase interpolator operable to select a phase signal from among the one or more phase signals output by the multiphase VCO, to produce an interpolated output signal having a desired frequency resolution.

High bandwidth phase locked loop (PLL) with feedback loop including a frequency divider

A phase interpolator is provided that, in one implementation, includes an output node, a plurality of phase input circuits, and a plurality of switches corresponding to the plurality of phase input circuits. Each phase input circuit is operable to receive a given phase signal. Each switch is in communication with a given phase input circuit and is operable to couple a given phase signal to the output node.

A frequency phase locked loop (FPLL) includes a first feedback loop coupled to a second feedback loop. The first feedback loop is configured to correct a phase offset of an output signal of the FPLL. The second feedback loop is configured to correct a frequency offset of the output signal of the FPLL.

Apparatus for low-jitter frequency and phase locked loop and associated methods

Apparatuses, methods, and systems for compensating baseline offset in a read channel of an analog storage device. The apparatus generally includes an AC-coupling circuit configured to transfer an analog signal from an analog storage device to the read channel, a configurable current device coupled to the AC-coupling circuit, comparator coupled to the AC-coupling circuit, and logic coupled to the configurable current device and the comparator, wherein the logic is adapted to configure said current device in response to an output of at least one of the AC-coupling circuit and the comparator. The method generally includes the steps of coupling an analog storage device and the read channel with an AC-coupling circuit, detecting a baseline or a component of an analog signal at a node downstream from the AC-coupling circuit, and configuring a current device to modify the analog signal in response to detecting the baseline or a component of the analog signal, wherein the current device is coupled to a node downstream from the AC-coupling circuit and upstream from a signal processor configured to operate on the analog signal.

Apparatus, method, and system for correction of baseline wander

A pre-compensation circuit comprises a clock delay generator that generates clock delay data based on a clock signal having a first clock rate. A reference clock delay unit receives the clock signal and generates reference clock delay information based on the first clock rate. A calibration unit receives the reference clock delay information and calibrates each of n clock delay units based on the reference clock delay information and a change in the first clock rate, wherein n is an integer greater than 1.

Precompensation circuit for magnetic recording

A phase locked loop (PLL) is provided. In one implementation, the PLL includes a feedback loop having a frequency multiplier and an integer divider to generate a divided signal. The PLL includes a re-sampling circuit operable to re-sample one or more digital pulses of the divided signal using one or more phase signals if a multiplication factor of the frequency multiplier does not divide evenly into the integer divisor.

Growing community of inventors

San Jose, CA, United States of America

Chi Fung Cheng