International Business Machines Corporation

Globalfoundries Inc.

Adeia Semiconductor Bonding Technologies Inc.

Tokyo Electron Limited

Stmicroelectronics Gmbh

Jsr Corporation

Elpis Technologies Inc.

Adeia Semiconductor Solutions LLC

Tokyo Eelctron Limited

Chi-Chun Liu

Kangguo Cheng

Cheng Chi

Yann Mignot

Nelson M Felix

Michael A Guillorn

Hsinyu Tsai

Ruilong Xie

Yann A M Mignot

Kristin Schmidt

Joy Cheng

Peng Xu

Fee Li Lie

Kafai Lai

Ekmini Anuja De Silva

Hsueh-Chung Chen

Chun Wing Yeung

Stuart A Sieg

John Christopher Arnold

Steven J Holmes

Matthew Earl Colburn

Daniel Sanders

Muthumanickam Sankarapandian

Yongan Xu

Zhenxing Bi

Sean David Burns

Jed Walter Pitera

Mary Claire Silvestre

Tenko Yamashita

Junli Wang

Shogo Mochizuki

Hemanth Jagannathan

Ankit Vora

Hao Tang

Robin Hsin Kuo Chao

Yi Song

Kisup Chung

Ananthan Raghunathan

Jassem Ahmed Abdallah

Isabel C Estrada-Raygoza

Ashim Dutta

Melia Tjio

Anuja E DeSilva

Robin Hsin-Kuo Chao

Alexander Reznicek

Chih-Chao Yang

Chen Zhang

Chun-chen Yeh

Hong He

Joshua T Smith

Sanjay C Mehta

Hosadurga K Shobha

Hiroyuki Miyazoe

Terry Allen Spooner

Xuefeng Liu

Markus Brink

Robert L Bruce

Shyng-Tsong Chen

Chiahsun Tseng

Shawn Peter Fetterolf

Wenhui Wang

Dominik Metzler

Gurpreet Singh

Jie Yang

Alexander M Friz

Luciana Meli

Sylvie M Mignot

Bassem M Hamieh

Lin Hu

Hongyun Cottle

Theodorus E Standaert

Chanro Park

Sivananda K Kanakasabapathy

Soon-Cheon Seo

Su Chen Fan

Koichi Motoyama

Yunpeng Yin

Dario Leonardo Goldfarb

Indira P Seshadri

Teddie Peregrino Magbitang

Akiteru Ko

Charles Thomas Rettner

Allen H Gabor

Hoa D Truong

Karen Elizabeth Petrillo

Somnath Ghosh

Jing Guo

Nihar Mohanty

Hitoshi Osaki

Liying Jiang

Alan C Thomas

Cody John Murray

Martha Inez Sanchez

Noel Arellano

Jennifer A Oakley

Gregory S Doerk

Daiji Kawamura

Sean D Burns

A semiconductor device includes a conductive line disposed within a dielectric layer, a metal layer disposed over and in direct contact with the conductive line, and a metallization layer disposed over the metal layer such that a protruding segment of the metal layer acts as an interface between the conductive line and the metallization layer. The conductive line is copper (Cu) and the metal layer is ruthenium (Ru). The Ru metal layer includes an upper metal layer section and a lower metal layer section.

Dual-metal ultra thick metal (UTM) structure

A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern includes hardmask fins of three mutually selectively etchable compositions. Some of the fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color and that leaves at least one fin of the first color behind. The fins of the second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.

Alternating hardmasks for tight-pitch line formation

A method of semiconductor manufacture comprising forming a plurality of first mandrels as the top layer of the multi-layered hard mask and forming a first spacer around each of the plurality of first mandrels. Removing the plurality of first mandrels and cutting the first spacer to form a plurality of second mandrels. Forming a second spacer around each of the plurality of second mandrels and forming a first self-aligned pattern that includes a plurality of third mandrels. Removing the plurality of second mandrels and the second spacer and etching the multi-layered hard mask to transfer the first-self aligned pattern to a lower layer of the multi-layered hard mask. Forming a second self-aligned pattern, wherein the second self-aligned pattern is intermixed with the first self-aligned pattern and etching the first self-aligned pattern and the second self-aligned pattern into the conductive metal layer.

Structure and method to pattern pitch lines

A device includes: a first dielectric material; a first metal line in the first dielectric material; a second dielectric material disposed on the first dielectric material and the first metal line; a second metal line in the second dielectric material; and a plurality of metal vias disposed on a same level and connecting the first metal line and the second metal line, wherein the plurality of metal vias comprise a first top via and a bottom via having different sidewall profile angles.

Dual color via patterning

A semiconductor structure comprises a plurality of gate structures alternately stacked with a plurality of channel layers, and a plurality of spacers disposed on lateral sides of the plurality of gate structures. The respective ones of the plurality of spacers comprise a profile having a first portion comprising a first shape and a second portion comprising a second shape, wherein the first shape is different from the second shape.

Inner spacer formation for nanosheet transistors

A method of manufacturing a semiconductor device is provided. The method includes forming a plurality of metal lines on substrate, forming a sacrificial dielectric material layer between the metal lines, forming a hardmask over at least one of the metal lines, etching at least one of the metal lines that is not covered by the hardmask, treating the sacrificial dielectric material layer to soften the layer. The method also includes removing the treated sacrificial dielectric material layer.

Spin on scaffold film for forming topvia

A semiconductor structure includes a set of mandrel lines and a set of non-mandrel lines disposed on a hardmask in an alternating pattern. Spacers are disposed between adjacent mandrel lines and non-mandrel lines. The spacers include a composition which exhibits an etch rate greater than an etch rate of the mandrel lines and the non-mandrel lines.

Fabrication of back-end-of-line interconnects

Structures are provided that include a metal-insulator-metal capacitor (MIMCAP) present in the back-end-of-the-line (BEOL). The MIMCAP includes at least one of the bottom electrode and the top electrode having a via portion and a base portion that is formed utilizing a subtractive via etch process. Less via over etching occurs resulting in improved critical dimension control of the bottom and/or top electrodes that are formed by the subtractive via etch process. No bottom liner is present in the MIMCAP thus improving the resistance/capacitance of the device. Also, and in some embodiments, a reduced foot-print area is possible to bring the via portion of the bottom electrode closer to the top electrode.

Subtractive via etch for MIMCAP

A resistance switching RAM logic device is presented. The device includes a pair of resistance switching RAM cells that may be independently programed into at least a low resistance state (LRS) or a high resistance state (HRS). The resistance switching RAM logic device may further include a shared output node electrically connected to the pair of resistance switching RAM cells. A logical output may be determined from the programmed resistance state of each of the resistance switching RAM cells.

Non volatile resistive memory logic device

A method of making a semiconductor device includes depositing an oxide material on a patterned mask arranged on a substrate. The method further includes removing a portion of the oxide material such that the patterned mask is exposed. The method also includes removing the patterned mask such that the substrate is exposed between areas of remaining oxide material.

Direct extreme ultraviolet lithography on hard mask with reverse tone

A security region is provided. The security region includes a plurality of parallel conductive lines on a substrate, wherein each of the parallel conductive lines has a width and includes a bend, and wherein at least a portion of the plurality of parallel conductive lines is discontinuous, and an electrically insulating material between each adjacent pair of parallel conductive lines.

Embedded chip identification formed by directed self-assembly

A method for fabricating a semiconductor device includes forming a plurality of mandrel cuts from a first set of mandrels of a base structure using lithography, surrounding the first set of mandrels and a second set of mandrels of the base structure with spacer material to form mandrel-spacer structures, forming a flowable material layer on exposed surfaces of the mandrel-spacer structures, and performing additional processing, including forming a plurality of dielectric trenches within the base structure based on patterns formed in the flowable material layer.

Litho-etch-litho-etch with self-aligned blocks

A self-priming resist may be formed from a first random copolymer forming a resist and a polymer brush having the general formula poly(A-r-B)-C-D, wherein A is a first polymer unit, B is a second polymer unit, wherein A and B are the same or different polymer units, C is a cleavable unit, D is a grafting group and r indicates that poly(A-r-B) is a second random copolymer formed from the first and second polymer units. The first random copolymer may be the same or different from the second random polymer. The self-priming resist can create a one-step method for forming an adhesion layer and resist by using the resist/brush blend.

Self-priming resist for generic inorganic hardmasks

A method of forming a semiconductor structure includes forming a memorization layer over a substrate, forming a first self-aligned double patterning (SADP) stack including a first organic planarization layer (OPL), masking layer, set of mandrels, and set of spacers, and forming a patterned memorization layer by transferring a first pattern of the first set of spacers to the memorization layer. The method also includes forming a second SADP stack comprising a second OPL, masking layer, set of mandrels, and set of spacers, and forming an array of pillars by transferring a second pattern of the second set of spacers to the patterned memorization layer. The first and second OPL and the first and second sets of mandrels are a spin-on coated OPL material, and the memorization layer and first and second masking layers are a material configured for removal selective to the spin-on coated OPL material.

Back-end-of-line compatible processing for forming an array of pillars

Growing community of inventors

Altamont, NY, United States of America

Chi-Chun Liu