Sunasic Technologies Limited

Promos Technologies, Inc

Chi Chou Lin

Zheng Ping He

Fang-Yu Yeh

Chia-Yao Chen

Chuang-Hsiang Chen

Hao-Jyh Liu

Chung Hao Hsieh

A biometric security device for digital key storing is disclosed. The biometric security device includes a biometric information fetching module and a processing module. The processing module has a nonvolatile storage unit and a processing unit. The nonvolatile storage unit includes a secure storage unit and a general storage unit. The biometric security device with a secure electronic key designed for storing secret data utilizes both TrustZone&#x2122; technology (or similar technology) and biometric authentication. Thus, it can provide the flexibility for multiple users or applications to use the biometric security device or any equipment the biometric security device mounted in without compromising the safeguard of the data stored therein.

Biometric security device

A secure electronic device is disclosed. The secure electronic device includes a first core processing unit, a secure boot Read-Only Memory, a first non-volatile memory, a first volatile memory and a first communication interface. A new framework based on the secure electronic device with built-in security is able to safeguard intellectual property for the developers and further improves the security of the secure electronic device. Thus, more developers can launch their programs or services without being stolen or tampered by an unauthorized party.

Secure electronic device

A noised-reduced capacitive image sensor and a method operating the capacitive image sensor are provided. The capacitive image sensor includes: a number of capacitive sensing units forming an array, each capacitive sensing unit for transforming a distance between a portion of a surface of an approaching finger and a top surface thereof into an output electric potential, wherein a value of the output electric potential is changed by a driving signal applied to the sensing unit; at least one sample-and-hold circuit for capturing and retaining different output electric potentials; at least one signal conditioning circuit, each comprising at least one differential amplifier for amplifying a difference between two electric potentials retained by the sample-and-hold circuit; and a driving source, for providing the driving signal to the capacitive sensing units.

Noise reduced capacitive image sensor and method operating the same

A noised-reduced capacitive image sensor and a method operating the capacitive image sensor are provided. In order to generate a noise-reduced image of a fingerprint, the capacitive image sensor has an array of capacitive sensing units which each has a protective layer; a sensing electrode; a voltage follower; a comparative capacitor; and a bias voltage supply circuit. The comparative capacitor, a portion of the bias voltage supply circuit, and the voltage follower are formed in an isolated well which is configured in such a way that current is able to be prevented from flowing across an interface in the isolated well and surrounding structures. The driving source is connected to a bulk node of the isolated well such that well potential of the isolated well equals to the output electric potential of a driving source.

Noise-reduced capacitive image sensor and method operating the same

A capacitive image sensor with noise reduction feature and a method operating the capacitive image sensor are provided. The capacitive image sensor includes: a number of capacitive sensing units, arranged in a form of an array, wherein each of the number of capacitive sensing units switches between three states: sensing state, idle state, and emitting state; a driving source, for providing a driving signal to an adjacent finger overlying the number of capacitive sensing units through the number of capacitive sensing units which are in the emitting state; a number of driving switches, each connected between one of the number of capacitive sensing units and the driving source; and a control and timing logic, connected to each of the number of driving switches, for controlling the state of each of the number of capacitive sensing units.

Capacitive image sensor with noise reduction feature and method operating the same

A fingerprint sensing device and a method operating the fingerprint sensing device are provided. The fingerprint sensing device includes at least one sensing core, a system unit, at least one switching unit and a charge holding unit. The switching unit is connected between the sensing core and the system unit to provide four different operation states: a normal state; an isolation state; a drive-up state; and a drive-down state. A voltage shift between the finger and the sensing core is generated by controlling the switching unit to perform different operation states in various orders.

Fingerprint sensing device and method operating the same

A capacitive image sensor with noise reduction feature and a method operating the capacitive image sensor are provided. The capacitive image sensor includes: a number of capacitive sensing units forming an array, each capacitive sensing unit for transforming a distance between a portion of a surface of an approaching finger and a top surface thereof into an output electric potential, wherein a value of the output electric potential is changed by a driving signal coupled on the finger; at least one sample-and-hold circuit for capturing and retaining different output electric potentials; at least one signal conditioning circuit, each comprising: at least one differential amplifier for amplifying a difference between two electric potentials retained by the sample-and-hold circuit; and a driving source, for providing the driving signal to the finger.

A capacitive image sensor and a method for operating the capacitive image sensor are provided. The capacitive image sensor has an array of capacitive sensing units for transforming a distance between each of the capacitive sensing units and a surface of an adjacent finger into an output electric potential. The capacitive sensing unit comprises: a protective layer; a first sensing plate, formed under the protective layer; a second sensing plate, formed under the first sensing plate; an active semiconductor circuitry, formed under the second sensing plate and connected to the first and second sensing plates; at least one first insulating layer, formed between the first sensing plate and the second sensing plate; and at least one second insulating layer, formed between the second sensing plate and the active semiconductor circuitry.

Capacitive image sensor and method for operating the same

A capacitive fingerprint sensor which includes capacitive sensing units is disclosed. Each of the capacitive sensing unit includes a sensing electrode; a first switch; a voltage follower; and a reference capacitor. The voltage follower includes an adjustable current source, for providing at least two distinct current levels; and a MOS transistor. The MOS transistor includes a source node, connected to ground via the adjustable current source and serves as an output node of the voltage follower; a gate node, connected to the sensing electrode and serves as an input node of the voltage follower; a drain node, connected to a power source, for providing power to the voltage follower; and a bulk node, connected to the source node.

Noise reduced capacitive fingerprint sensor and capacitive sensing unit included therein

A Printed Circuit Board Assembly (PCBA) for forming an enhanced biometric module and a method for manufacturing the PCBA are disclosed. The method includes the steps of providing a PCB, a biometric sensing chip and SMDs; mounting the biometric sensing chip on the PCB with each bonding pad being electrically linked to one corresponding first contact pad; mounting the SMDs on second contact pads which are electrically linked thereto, respectively; and forming a protection layer. The present invention takes advantages of compact size of small conductive elements to avoid cracks in the protection layer.

Printed circuit board assembly forming enhanced biometric module and manufacturing method thereof

A chip with I/O pads on the peripheries and a method making the chip is disclosed. The chip includes: a substrate; a first metal layer, formed above the substrate; an inter-metal dielectric layer, formed above the first metal layer, having concave portions formed along the peripheries of the chip so that a portion of the first metal layer is exposed to form an input-output (I/O) pad in each of the concave portions which are spaced apart from each other; and a passivation layer, formed above the second metal layer without covering the concave portions so that specific circuits are formed by the first metal layer and the second metal layer, respectively. By changing the I/O pad from the top of the chip to the peripheries, the extra thickness of the packaged chip caused by wire bonding in the prior arts can be reduced.

Chip with I/O pads on peripheries and method making the same

A method for manufacturing a semiconductor device that comprises defining a semiconductor substrate, forming a gate oxide on the semiconductor substrate, forming a polycrystalline silicon layer over the gate oxide, forming a tungsten silicide layer over the polycrystalline silicon layer; providing a mask over the tungsten silicide layer, defining the mask to expose at least one portion of the tungsten silicide layer, etching the exposed tungsten silicide layer with a first etchant, wherein some tungsten silicide layer remains, etching the remaining tungsten silicide layer with a second etchant to expose at least one portion of the polycrystalline silicon layer, annealing the tungsten silicide layer, etching the exposed polycrystalline silicon layer, and oxidizing sidewalls of the tungsten silicide layer and the polycrystalline silicon layer.

Two-step GC etch for GC profile and process window improvement

A method of manufacturing a semiconductor device is provided. First, a well region is formed in a substrate and then a mask layer is formed over the substrate. The mask layer and the substrate are patterned to form a first opening in the substrate. Thereafter, a threshold voltage adjustment process is performed. A gate dielectric layer, a first conductive layer and a second conductive layer are sequentially formed inside the first opening. The second conductive layer completely fills the first opening. A portion of the first conductive layer and the second conductive layer are removed so that the upper surface of the first conductive layer and the second conductive layer is slightly below the upper surface of the substrate and hence forms a second opening. A cap layer is formed in second opening and then the mask layer is removed. A source/drain region is formed in the substrate on each side of the first conductive layer. An inter-layer dielectric layer is formed over the substrate. Finally, using the cap layer as a self-aligned mask, a contact opening is formed in the inter-layer dielectric layer.

Growing community of inventors

Taipei, Taiwan

Chi Chou Lin