Texas Instruments Corporation

Chi-Chien Ho

Ashesh Parikh

Thomas John Smelko

William R McKee

Rajni J Aggarwal

A method to adjust transistor gate geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to form a reticle. A method to adjust transistor geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to compensate for transistor turn on voltage drop off where the transistor gate crosses the isolation/active interface.

Method to improve transistor matching

A method of computational lithography includes providing through-focus critical dimension (CD) curves at a range of different focus values (Bossung curves) for a plurality of feature types that include different ratios of line width to space width. Using software run on a computing device, it is determined if there is at least one marginal feature type from the plurality of feature types based an image tool capability and a predetermined process specification affected by at least one of the plurality of feature types. Provided a marginal feature type is determined to be present, at least the marginal feature type(s) is upsized. A degree of upsizing increases as a curvature of the Bossung curves increases. A computational lithography model is compiled including the upsizing.

Computational lithography with feature upsizing

A single polysilicon memory cell (,) provides a positive low programming and erase voltage together with a small cell size and includes P substrate (,) and P-well (,) formed within P substrate (,). NMOS transistor (,) is formed within P-well (,). N,control gate (,) is formed in P-well (,) and includes punch-through implant region (,). NMOS transistor (,) and N,control gate (,) have in common electrically isolated polysilicon gate (,) for operating as a floating gate in common with NMOS transistor (,) and N,control gate (,). N,control gate (,) includes P-channel punch-through implant (,) for increasing the capacitive coupling ratio. This improves programming and erasing efficiency within single polysilicon memory cell (,).

Method of fabricating and operating single polysilicon flash EEPROM with low positive programming and erasing voltage and small cell size

A single polysilicon memory cell (10) provides a positive low programming and erase voltage together with a small cell size and includes P substrate (12) and P-well (14) formed within P substrate (12). NMOS transistor (16) is formed within P-well (14). N.sup.+ control gate (26) is formed in P-well (14) and includes punch-through implant region (26). NMOS transistor (16) and N.sup.+ control gate (26) have in common electrically isolated polysilicon gate (22, 32) for operating as a floating gate in common with NMOS transistor (16) and N.sup.+ control gate (26). N.sup.+ control gate (26) includes P-channel punch-through implant (34) for increasing the capacitive coupling ratio. This improves programming and erasing efficiency within single polysilicon memory cell (10).

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Plano, TX, United States of America

Chi-Chien Ho