Andes Technology Corporation

Arm Technology (China) Co. Ltd

Mediatek Corporation

Chi-Chang Lai

Hsin-Ming Chen

Chuan-Hua Chang

Chun-Chang Yu

Yuan-Yuan Shih

Chi-Ming Li

Processing circuitry may support a secure domain and a less secure domain, where secure information associated with a secure software process is prevented from being accessed by a less secure software process in the less secure domain. Shared resource is accessible to both secure and less secure software processes. In response to detection of an anomaly condition, allocation policy for the shared resource is switched from a shared allocation policy to a secure-biased allocation policy. The secure-biased allocation policy has a stronger bias of resource allocation to secure software processes than the shared allocation policy.

Allocation policy for shared resource accessible in both secure and less secure domains

Circuitry comprises processing circuitry to process program instructions, in which the program instructions are stored by storage circuitry and the processing circuitry comprises execute-in-place processing circuitry configured to execute the program instructions from the storage circuitry; a prefetch buffer to store program instructions for execution by the processing circuitry; prefetch circuitry to control prefetching of program instructions to the prefetch buffer and to select a next instruction for prefetching; and replacement circuitry to control deletion of instructions from the prefetch buffer to provide storage for newly prefetched program instructions; in which one or both of the prefetch circuitry and the replacement circuitry are configured so that one or both of a selection operation by the prefetch circuitry of a next program instruction for prefetching, and a deletion operation to delete an instruction from the prefetch buffer by the replacement circuitry is dependent upon previously executed program instructions and a prediction of future program instructions to be executed.

Circuitry and method for selectively controlling prefetching of program instructions

A computer system includes a cache unit and a first processing unit. The first processing unit runs a first program thread, and performs an instruction to store information of a signal change event into the cache unit through a cache stashing operation, where the signal change event is initiated by the first program thread for alerting a second program thread.

Computer system for notifying signal change event through cache stashing

A secure protection method executed by a processor is provided. The secure protection method includes the following steps: Perform a security checking before or after executing an instruction according to an instruction security attribute (ISA) of the instruction and a security attribute (SA) of an operational event (OE); and ignore the OE, defer the OE, or raise a security exception when the security checking fails. The OE is generated as a side effect when the processor fetches or executes the instruction, or generated as a monitoring result on the instruction, or generated in response to an external input of the processor.

Secure protection processor and method including comparing an instruction security attribute of an instruction and a security attribute of an operational event

The present invention discloses a method for software-hardware authentication of an electronic apparatus includes receiving a challenge string (CS) from the electronic apparatus through a challenge string input port (CSIP). The challenge string is a string of trace data generated according to some operations of software running on the electronic apparatus. An authentication result for use in an authentication process for the software to authenticate a hardware unit of the electronic apparatus or for the hardware unit to authenticate the software is generated according to the string of the trace data. The authentication process is performed according to the generated authentication result.

Method and apparatus for software-hardware authentication of electronic apparatus

An interrupt controller coupled to a plurality of processors is provided to rout at least one interrupt request event to at least one of the processors. The interrupt controller includes a receiving circuit and a controlling circuit. The receiving circuit receives at least one interrupt input, and the controlling circuit, generates the at least one interrupt request event based on the received at least one interrupt input and routes the at least one interrupt request event generated to the at least one of the processors. The plurality of processors including at least a first processor and a second processor, the first and second processors arranged to process interrupt request event(s), and the controlling circuit is arranged to withdraw/cancel assertion of an interrupt request event that has been transmitted to the first processor.

Interrupt controller, apparatus including interrupt controller, and corresponding methods for processing interrupt request event(s) in system including processor(s)

A bus apparatus is provided, which includes a bus master and a bus slave coupled to the bus master through a bus interface. When the bus master sends a bus transaction to the bus slave, the bus slave executes the bus transaction. The bus transaction is speculative by default. The command of the bus transaction indicates whether the bus transaction is a write transaction or a read transaction. When the bus transaction is a write transaction, the bus slave stores the write data of the bus transaction at the address of the bus transaction. When the bus transaction is a read transaction, the bus slave responds the bus transaction with a read data stored at the address of the bus transaction. The bus slave informs the bus master that the bus slave will not recognize further bus transactions in a specific period of time by asserting a bus wait signal.

Bus apparatus with default speculative transactions and non-speculative extension

A power scaling unit (PSU) of an electronic system is provided. The PSU includes a software programming interface (SPI) and a PSM. The SPI receives a transaction through software programming. The PSM receives the transaction from the SPI and controls a power driving element (PDE) of the electronic system to change an output of the PDE provided to a function unit of the electronic system according to the transaction. The output of the PDE is an operating voltage or an operating clock signal of the function unit. The transaction includes a command defining a power scaling operation to be performed by the PSM, a parameter used by the operation, and an event mask specifying an event which triggers the operation.

Power scaling module and power scaling unit of an electronic system having a function unit in a standby state which is insensitive to change in frequency or voltage during synchronization

An in-circuit debugging (ICD) system includes at least a first target processor, an embedded debug mode with a debug information memory (DIM), a debug host, and an ICD bridge. The first target processor has an embedded debug module (EDM) and performs a program code in normal mode, where the first EDM controls the first target processor in debug mode. The DIM stores debug information for debugging in debug mode, and is invisible to the first target processor when the first target processor operates in normal mode. The debug host has debug software, and is utilized for debugging the program code by using the debug information in debug mode. The ICD bridge has a host debug module (HDM) coupled to the first EDM, and is coupled between the first target processor and the debug host and utilized for bridging information communicated between the first target processor and the debug host.

Growing community of inventors

Hsinchu County, Taiwan

Chi-Chang Lai