Taiwan Semiconductor Manufacturing Comp. Ltd.

Global Unichip Corporation

University of California

National Taiwan University

Chewn-Pu Jou

Huan-Neng Chen

Lan-Chou Cho

Feng Wei Kuo

Fu-Lung Hsueh

Feng-Wei Kuo

William Wu Shen

Ho-Hsiang Chen

Hsieh-Hung Hsieh

Tzu-Jin Yeh

Wen-Shiang Liao

Ying-Ta Lu

Min-Hsiang Hsu

Stefan Rusu

Kuang-Kai Yen

Robert Bogdan Staszewski

Chia-Chung Chen

Yen-Jen Chen

Hsien-Yuan Liao

Hsiao-Tsung Yen

Chih-Tsung Shih

Yi-Hsuan Liu

Cheng-Tse Tang

Chen-Hua Douglas Yu

Chien-Hsun Lee

Yu-Ling Lin

Shuo-Mao Chen

Weiwei Song

Tsung-Hsiung Lee

Chan-Hong Chern

Hung-Yi Kuo

Chin-Wei Kuo

Jun-De Jin

Chi-Feng Huang

Sally Liu

Chung-Shi Liu

Hao-Yi Tsai

Cheng-Chieh Hsieh

Chung-Ming Weng

Mei-Show Chen

Min-Jer Wang

Tien-I Bao

Jiun Yi Wu

Chih-Chang Lin

Tsung-Yuan Yu

Hung-Chih Lin

Hao Chen

Ching-Nen Peng

Jiun-Yi Wu

Hua-Kuei Lin

Jack Liu

Chih-Hang Tung

Min-Chie Jeng

Ming Hsien Tsai

Tze-Chiang Huang

Shyh-An Chi

Chien-Jung Wang

Chi-Hsien Lin

Shu Fang Fu

Chin-Yuan Huang

Kai-Yun Lin

Seyednaser Pourmousavian

Clement Hsingjen Wann

Chih-Hsin Ko

Yu-Hsiang Hu

Chao-Ching Cheng

Yun-Han Lee

Chun-Chieh Lu

Hsing-Kuo Hsia

Felix Ying-Kit Tsui

Shen-Iuan Liu

Wei-Li Chen

Ming-Hsien Tsai

Che-Hsiang Hsu

Po-Wen Chiu

Harry-Hak-Lay Chuang

Der-Chyang Yeh

Chuei-Tang Wang

Yung-Chow Peng

Hsiu-Jen Lin

Tai-Chun Huang

Ming-Che Ho

Hui Yu Lee

Chih-Ping Chao

Yung-Hsu Chuang

Sa-Lly Liu

Jia-Liang Chen

Yung-Jr Hung

Mill-Jer Wang

Ming-Hsiang Song

Feng Yuan

Cheng-Wei Luo

Hau-Yan Lu

Tse-Hua Lu

Jinn-Yeh Chien

Masoud Babaie

Cheng Yuan Hsiao

Yanghyo Kim

Chwei-Ching Chiu

The present disclosure relates to optical waveguide termination devices. In some embodiments, an optical waveguide termination device is coupled to an end of an optical waveguide. The optical waveguide termination device is a tapered structure. In various embodiments, an optical absorption rate of the tapered structure is increased to enhance a termination efficiency. The optical absorption is increased by highly-doped material, multi-layer structure, different cladding, and periodic structure. The enhancement of the termination efficiency benefits size reduction of the tapered structure.

Optical waveguide termination

A package structure comprises photonic dies and an interposer structure. Each photonic die includes a dielectric layer and a first grating coupler embedded in the dielectric layer. The interposer structure is disposed below the photonic dies. The interposer structure includes an oxide layer and a second grating coupler embedded in the oxide layer. The photonic dies are optically coupled through the first grating couplers of the photonic dies and the second grating coupler of the interposer structure.

Package structure having grating coupler and manufacturing method thereof

The present disclosure provides semiconductor devices and photonic circuits. The semiconductor device includes a substrate and an optical modulator disposed on the substrate. The optical modulator includes a first electrical coupling portion having a first type doping, a second electrical coupling portion having a second type doping, and an optical coupling portion disposed between the first electrical coupling portion and the second electrical coupling portion, where the optical coupling portion includes an intrinsic semiconductor. The optical modulator is configured to receive a first voltage through the first electrical coupling portion and the second electrical coupling portion to decrease a resonant wavelength of the optical modulator.

Semiconductor device, photonic circuit and method for adjusting resonant wavelength of optical modulator

The present disclosure provides a light detecting device. The light detecting devices includes an insulating layer, a silicon layer, a light detecting layer, N first doped regions and M second doped regions. The silicon layer is disposed over the insulating layer. The light detecting layer is disposed over the silicon layer and extends within at least a portion of the silicon layer. The first doped regions have a first dopant type and are disposed within the light detecting layer. The second doped regions have a second dopant type and are disposed within the light detecting layer. The first doped regions and the second doped regions are alternatingly arranged. M and N are integers equal to or greater than 2.

Light detecting device, optical device and method of manufacturing the same

An optical device for coupling light propagating between a waveguide and an optical transmission component is provided. The optical device includes a taper portion and a grating portion. The taper portion is disposed between the grating portion and the waveguide. The grating portion includes rows of grating patterns. A first size of a first grating pattern in a first row of grating patterns is larger than a second size of a second grating pattern in a second row of grating patterns. A first distance between the first row of grating patterns and the waveguide is less than a second distance between the second row of grating patterns and the waveguide.

Optical device for coupling light and method for fabricating the same

A device includes an optical isolator disposed between adjacent optical waveguides along a direction. The optical isolator has vertical or horizontal dimensions that are different than at least one of the optical waveguides. The vertical and horizontal dimensions are greater than vertical and horizontal dimensions of at least one of the waveguides. In various embodiments, the structure of the optical isolator can be a planar structure, a columnar periodic structure, or a grating structure. The material of the optical isolator can be a metallic material or a dielectric material. In some embodiments, the optical isolator and the optical waveguides are used to enhance the performance of an optical multiplexing device.

Optical isolator integrated with optical devices

A method of verifying an integrated circuit stack includes adding a first dummy layer to a first contact pad of a circuit, wherein a location of the first dummy layer is determined based on a location of a second contact pad of a connecting substrate. The method further includes converting the first dummy layer location to the connecting substrate. The method further includes adjusting the first dummy layer location in the circuit in response to a determination that the first dummy layer location is misaligned with the second contact pad. The method further includes performing a first layout versus schematic (LVS) check of the connecting substrate including the first dummy layer in response to a determination that the first dummy layer is aligned with the second contact pad.

Integrated circuit stack verification method and system for performing the same

A semiconductor structure includes a semiconductor substrate, a semiconductor device and a heating structure. The semiconductor substrate includes a device region and a heating region surrounding the device region. The semiconductor device is located on the device region. The heating structure is located on the heating region and includes an intrinsic semiconductor area, at least one heating element and at least one heating pad. The intrinsic semiconductor area is surrounding the semiconductor device. The at least one heating element is located at a periphery of the intrinsic semiconductor area. The at least one heating pad is joined with the at least one heating element, wherein the at least one heating pad includes a plurality of contact structures, and a voltage is supplied from the plurality of contact structures to control a temperature of the at least one heating element.

Method of fabricating semiconductor structure with heating element

An integrated circuit package integrates a photonic die (oDie) and an electronic die (eDie). More specifically, the integrated circuit package may include a plurality of redistribution layers communicatively coupled to at least one of the oDie and/or the eDie, where molded material at least partially surrounds the at least one of the oDie and/or the eDie.

Photonics integrated circuit package

A semiconductor structure according to the present disclosure includes a buried oxide layer, a first dielectric layer disposed over the buried oxide layer, a first waveguide feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first waveguide feature, a third dielectric layer disposed over the second dielectric layer, and a second waveguide feature disposed in the second dielectric layer and the third dielectric layer. The second waveguide feature is disposed over the first waveguide feature and a portion of the second waveguide feature vertically overlaps a portion of the first waveguide feature.

Optical waveguide apparatus and method of fabrication thereof

In an embodiment, a circuit includes: a transformer defining an inductive footprint within a first layer; a grounded shield bounded by the inductive footprint within a second layer separate from the first layer; and a circuit component bounded by the inductive footprint within a third layer separate from the second layer, wherein: the circuit component is coupled with the transformer through the second layer, and the third layer is separated from the first layer by the second layer.

Systems and methods for shielded inductive devices

A benchmark device and a method for evaluating a semiconductor wafer are provided. The benchmark device includes a first grating coupler, a second grating coupler and a waveguide. The waveguide has a least one bending section and is arranged in communication with the first grating coupler and the second grating coupler. The bending section comprises a first region having a first width and a first height, and a second region having a second width and a second height, wherein the first region is surrounded by the second region, and the second width decreases gradually from a first end of the bending section to a second end of the bending section.

Benchmark device and method for evaluating a semiconductor wafer

Among other things, a method of fabricating an integrated electronic device package is described. First trace portions of an electrically conductive trace are formed on an electrically insulating layer of a package structure, and vias of the conductive trace are formed in a sacrificial layer disposed on the electrically insulating layer. The sacrificial layer is removed, and a die is placed above the electrically insulating layer. Molding material is formed around exposed surfaces of the die and exposed surfaces of the vias, and a magnetic structure is formed within the layer of molding material. Second trace portions of the electrically conductive trace are formed above the molding material and the magnetic structure. The electrically conductive trace and the magnetic structure form an inductor. The electrically conductive trace may have a coil shape surrounding the magnetic structure. The die may be positioned between portions of the inductor.

Integrated fan-out package with 3D magnetic core inductor

A method of making a semiconductor device includes forming a first transmission line over a substrate. The method includes forming a second transmission line over the substrate. The method further includes depositing a high-k dielectric material between the first transmission line and the second transmission line, wherein the high-k dielectric material partially covers each of the first transmission line and the second transmission line. The method further includes depositing a dielectric material directly contacting the high-k dielectric material, wherein the dielectric material has a different dielectric constant from the high-k dielectric material, and the dielectric material directly contacts the first transmission line or the second transmission line.

Semiconductor device and methods, where first and second transmission lines are surrounded by first and second high-k dielectric materials

An interconnect structure includes a dielectric block, a first conductive plug, a second conductive plug, a substrate, a first conductive line, and a second conductive line. The first conductive plug and the second conductive plug are surrounded by the dielectric block. The substrate surrounds the dielectric block. The first conductive line is connected to the first conductive plug and is in contact with a top surface of the dielectric block. The second conductive line is connected to the second conductive plug.

Interconnect structure having conductor extending along dielectric block

Growing community of inventors

Hsinchu, Taiwan

Chewn-Pu Jou