Industrial Technology Research Institute

Cheun-Song Lin

Bor-Chuan Kuo

Lie-Der Lin

Rong-Chung Chen

Shu-Wei Wang

Well-Chen Chua

Shih-Pao Sun

A bit-reversing method and system are disclosed for linearly scaling an image frame horizontally, vertically or both. The system includes a counter circuit for outputting the current frame-column number of the currently scanned pixel and the current frame-row number of the currently scanned frame-row. The numbers are bit reversed in a converter circuit. The bit-reversed current frame-column number is compared in a comparator circuit to a horizontal scaling constant which equals the number of pixels to be discarded in each frame-row of the image frame. The bit-reversed current frame-row number is compared in the comparator circuit to a vertical scaling constant which equals the number of frame-rows of the image frame to be discarded. If the bit-reversed current frame-row number is greater than the vertical scaling constant then the comparator circuit outputs appropriate signals to a scaling controller and an address generator for storing the currently scanned frame-row in a frame buffer. Otherwise, the comparator circuit outputs appropriate signals for discarding the currently scanned frame-row. Likewise, if the bit-reversed current column number is greater than the horizontal scaling constant, the comparator circuit outputs appropriate signals to the scaling controller and address generator for storing the currently scanned pixel in the frame buffer. Otherwise, the comparator circuit outputs appropriate signals for discarding the currently scanned pixel.

Bit-reversing method and system for linear image scaling

A host computer, a graphics processor which receives and executes commands generated by the host computer, a display memory for storing display data, and a display device for displaying the display data are provided. A graphics context is also provided in which the parameters of a current image are stored. A processing unit for receiving and executing the graphics commands issued by the host computer and for converting the parameters stored in the graphics context into the display data, and a drawing unit for storing the display data in the display memory are also provided. Furthermore, a shared memory is provided which is directly accessible to the host computer so that it can write the parameters of a next graphics command into the shared memory while the graphics processor is executing a current command. The shared memory is also directly accessible to the graphics processor so that it can receive the parameters of the next graphics command to be executed directly from the shared memory. In a preferred embodiment, transfers of the graphics parameters between the graphics context and the shared memory are accomplished by employing a bit-block transfer method and a mask register stored in the graphics context.

Fast graphics control system capable of simultaneously storing and

A video display system includes a frame buffer comprising five sets of one or more VRAMs. An address generator for generating address locations in the frame buffer generates chip select, row select and column select address signals. Because the frame buffer comprises five sets of VRAMs, the generation of the address signals requires divide-by-five operations to be carried out. Accordingly, the address generator includes a unique divide-by-five circuit wherein the division is carried out by a sequence of additions and multiplications. In comparison to conventional systems, the video system of the present invention makes more efficient use of memory capacity in the frame buffer.

Memory architecture with graphics generator including a divide by five

A video display system includes a frame buffer includes five sets of one or more video random access memories. An address generator for generating address locations in the frame buffer generates ship select, row select and column select address signals. Because the frame buffer comprises five sets of video random access memories, the generation of the address signals requires divide-by-five operations to be carried out. Accordingly, the address generator includes a unique divide-by-five circuit wherein the division is carried out by a sequence of additions and multiplications. In comparison to conventional systems, the video system of the present invention makes more efficient use of memeory capacity in the frame buffer.

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Taichung, Taiwan

Cheun-Song Lin