Hynix Semiconductor Inc.

Skhynix Inc.

Cheul Hee Koo

Sam Kyu Won

Duck Ju Kim

Chang Won Yang

Byoung Young Kim

Byung Ryul Kim

Jun Rye Rho

Won Kyung Kang

A program method of a nonvolatile memory device includes a pre-program verify step for verifying a threshold voltage of a selected memory cell; a step of setting a bit line voltage of the selected memory cell according to the threshold voltage of the selected memory cell which is determined through the pre-program verify step; a step of applying a program voltage to the selected memory cell set with the bit line voltage; and a post-program verify step for verifying a programmed state of the selected memory cell applied with the program voltage.

Program method of nonvolatile memory device for having dense threshold voltage distribution by controlling voltage of bit line according to threshold voltage of memory cell

A semiconductor memory device includes: a memory array including a plurality of memory cells; and a peripheral circuit configured to change a voltage level of a bit line connected to a program target cell according to a threshold voltage of the program target cell among the memory cells during a program operation.

Semiconductor memory device with high threshold voltage distribution reliability method

The present technology relates to an electronic device, and more particularly, to a semiconductor device. The semiconductor device includes a peripheral circuit, a power output line connected to the peripheral circuit and configured to transmit an operation voltage to the peripheral circuit, a current compensator including an OP-amplifier connected to the power output line, and a capacitor connected between an output terminal of the OP-amplifier and the power output line.

Semiconductor device including current compensator

A nonvolatile memory device including a plurality of memory cells arranged at a region where a word line and a bit line cross each other, a voltage generator configured to generate a program voltage to apply to the word line by increasing the program voltage by an increment whenever a program loop is repeated, a current sensing check unit configured to compare a number of failed memory cells among the memory cells to first and second reference values, and a control logic configured to control the voltage generator to change the increment according to the comparison result of the current sensing check unit.

Nonvolatile memory device, operating method thereof, and data storage device having the same

A nonvolatile memory device includes a memory cell array configured to comprise a number of cell strings, a number of page buffers each coupled to the cell strings of the memory cell array through bit lines, and a bit line precharge circuit configured to precharge a selected bit line up to a voltage of a first level before one of the page buffers precharges the selected bit line.

Circuit for precharging bit line and nonvolatile memory device including the same

Disclosed are a circuit and a method for controlling redundancy in a semiconductor memory apparatus. The circuit includes a peripheral circuit redundancy control block and a memory bank redundancy control block. The peripheral circuit redundancy control block buffers and latches an external command to generate an internal command. The peripheral circuit redundancy control block also buffers and latches an external address to generate a global address by comparing the external address with a predetermined output signal of a fuse circuit. The memory bank redundancy control block receives the global address corresponding to the internal command to selectively activate a redundancy word line or a main word line, such that the fuse circuit is provided in the peripheral circuit redundancy control block.

Circuit for controlling redundancy in semiconductor memory apparatus

A nonvolatile memory device includes a memory cell array configured to include cell strings coupled between respective bit lines and a source line, a unilateral element coupled to the source line, and a negative voltage generation unit coupled to the unilateral element and configured to generate a negative voltage.

Nonvolatile memory device for preventing a source line bouncing phenomenon

A page buffer circuit comprises a bit line selection unit, a latch unit, and a bit line control unit. The bit line selection unit is configured to select a bit line coupled to memory cells. The latch unit comprises a plurality of latch circuits. The plurality of latch circuits is coupled to a sense node and configured to latch data to be programmed into the memory cells or store data from the memory cells. The bit line control unit is coupled to the sense node and configured to temporarily charge a voltage of the selected bit line in response to charge and transfer control signals or transfer the charged voltage to the selected bit line.

Page buffer circuit, nonvolatile memory device including the page buffer circuit, and method of operating the nonvolatile memory device

A page buffer circuit comprises a sense unit, a latch unit, and a bit line voltage control unit. The sense unit is configured to couple a bit line and a sense node in response to a sense control signal in response to the sense control signal. The latch unit includes a plurality of latch circuits configured to latch data programmed or to be programmed. The bit line voltage control unit is configured to classify program states of memory cells, coupled to the selected bit line, into first to ngroups by performing first to nverification operations after a first program operation of a program operation and is configured to control a voltage level of the sense control signal in order to transfer a bit line voltage to the selected bit line.

Page buffer circuit, nonvolatile device including the same, and method of operating the nonvolatile memory device

A semiconductor memory device, which includes a clock tree circuit for correcting the duty cycle of a clock. The device sets a beta ratio to cause a constant duty cycle by using a reference clock having a constant duty cycle in a test mode, and then applies the set beta ratio to a DLL clock outputted from a delay-locked loop. Then, when the duty cycle of the DLL clock, to which the beta ratio has been applied, is not constant, the duty cycle of the DLL clock is corrected in the delay-locked loop.

Clock tree circuit and semiconductor memory device using the same, and duty cycle correction method

An address path circuit with a row redundant scheme may include an address buffer for buffering an external address to output an internal address, a command buffer for buffering a plurality of external commands, a pre-latch unit for pre-latching the internal address from the address buffer using a specific one of the commands buffered by the command buffer to output a pre-latched internal address, a detector for detecting whether the pre-latched internal address from the pre-latch unit is a repaired address or normal address and outputting one or more detection signals as a result of the detection, an address latch unit for latching the internal address from the address buffer synchronously with a buffered clock to output a latched internal address, and a global address generator for receiving the detection signals from the detector and the latched internal address from the address latch unit and generating a global row address.

Address path circuit with row redundant scheme

A synchronous memory device having an output driver controller, comprises a DLL circuit for receiving an external clock and outputting an internal clock; an output driver for outputting data in synchronism with the internal clock; and an output driver controller for controlling operation of the output driver, wherein the output driver controller makes the output driver active after receiving from the DLL circuit a control signal indicating that the internal clock is locked and is in a stabilized state.

Growing community of inventors

Icheon-si, South Korea

Cheul Hee Koo