International Business Machines Corporation

Chetan Mehta

Charles Scott Graham

Harvey Gene Kiel

Jaya Srikrishnan

Victor Anthony Garibay

Thomas R Sand

Daniel Ernest Hurlimann

Fernando Pizzano

Ronald Leroy Billau

Maulin Ishwarbhai Patel

Jayeshkumar M Patel

Rick A Hamilton, Ii

Lee Anton Sendelbach

Tingdong Zhou

Travis James Pizel

Patrick John Sugrue

David Charles Boutcher

Doorlabh Panjwani

David Arlen Elko

Gregory Francis Pfister

David Lee Randall

Stephanie Maria Forsman

Daniel H Lepore

Venkatesh Sainath

Paul Edward Movall

David R Willoughby

Michael Anthony Perez

George Henry Ahrens, Jr

Mark G Atkins

John Daniel Upton

Michael Youhour Lim

Shawn Michael Lambeth

Milton Devon Miller, Ii

Kiet Anh Tran

Michael Anton Barenys

Jinu Joy Thomas

Salim Ahmed Agha

Kevin Gene Kehne

Ghadir Robert Gholami

Joel Gerald Goodwin

Tam D Bui

John W Doxtader

Bradley Ryan Harrington

Vlctor A Garibay

Manesh Patel

Keng-Hiup Ng

Lee Anton Sendelback

Amir Simon

Michal B Cohen

Kasturi Patel

Edward Woodrow Wild, Jr

Daniel Lepore

Structures and methods for directly testing a semiconductor wafer having micro-solder connections. According to one embodiment, a method forms a pattern of micro-solder connections coupled with a through substrate via (TSV) that can be directly tested by electrical probing, without the use of a testing interposer. According to another embodiment, a method tests the pattern of micro-solder connections. According to another embodiment, a novel electrical probe tip structure has contacts on the same pitch as the pattern of micro-solder connections.

3D chip testing through micro-C4 interface

Apparatuses, methods, program products, and systems are presented for guided cable management. An apparatus includes a cable module that detects a first end of a cable installed at a port of a first node, a first port module that determines whether the cable that is installed at the port is an expected cable for the port based on a cable mapping table, and a first indicator module that triggers a visual indicator at the port to visually confirm that the cable is the expected cable for the port. The apparatus includes a second port module that determines a port of a second node where a second end of the cable is expected to be installed and a second indicator module that triggers a visual indicator at the port to visually indicate that the second end of the cable is expected to be installed in the port.

Guided cable management

A computer-implemented method determines that a link operation associated with a first link, among the set of interface links in a computing system, has resulted in a first set of signal lanes, included in the first link, becoming unused. The method further includes determining a link configuration and selecting, based on the link configuration, a second link from among the interface links, and determining a second set of signal lanes, from among the unused signal lanes included in the first link, to include in the second link. The signal lanes to include in the second link are based on an attribute associated with the second link. The method further includes dynamically reconfiguring the signal lanes included in the second to set to be included in the lanes in the second link. Some computing systems include a lane routing device connected to signal lanes of links among the interface links.

Dynamic re-allocation of signal lanes

The embodiments relate to dynamically re-allocating lanes of a computer bus. A computer system having a processor in communication with a module is booted. Allocation of lanes among adapters in communication with connectors of the computer bus is controlled at boot-time and, in response to detection of an additional adapter received after boot-time, an additional allocation of lanes to the additional adapter is dynamically controlled. The additional allocation includes allocating unallocated lanes to the additional adapter, and re-allocating at least one lane from the initial allocation in response to the unallocated lanes being insufficient.

Dynamic re-allocation of computer bus lanes

A system and method dynamically allocate address translation tables for direct memory access windows by donating logical memory blocks to allocate to the address translation tables. A dynamic address translation table allocation module dynamically changes the allocation of memory to the address translation tables without a platform or partition reboot. A portion of the dynamic address translation table allocation module may reside in the hypervisor and in the partition and communicate to dynamically allocate memory to the address translation tables. The dynamic address translation table allocation module in the partition may donate logical memory blocks to the hypervisor to increase the allocation of memory to the address translation tables.

Dynamic address translation table allocation

The embodiments relate to dynamically allocating lanes of a computer bus. A computer system is configured with a plurality of connectors in communication with a module, with each connector configured to receive a respective adapter. The module detects a presence of each primary and backup adapter present, and controls an initial allocation of lanes to each detected primary adapter for maximizing adapter functionality. After the initial allocation and in response to detecting a failure of at least one primary adapter, the module dynamically switches lanes from the failed adapter to at least one of the one or more remaining primary adapters and the backup adapter.

Switching allocation of computer bus lanes

The embodiments of the present invention relate to semiconductor device manufacturing, and more particularly to structures and methods of directly testing semiconductor wafers having micro-solder connections. According to one embodiment of the present invention, a method of forming a pattern of micro-solder connections coupled with a through substrate via (TSV) that can be directly tested by electrical probing, without the use of a testing interposer, is disclosed. According to another embodiment, a method of testing the pattern of micro-solder connections is disclosed. According to another embodiment, a novel electrical probe tip structure, having contacts on the same pitch as the pattern of micro-solder connections is disclosed.

An I/O adapter sharing mechanism in a logically partitioned computer system allows sharing a network I/O adapter between logical partitions in an efficient manner. A first logical partition owns (or controls) the I/O adapter, and a second logical partition desires to use (or share) the I/O adapter. An I/O adapter device driver that includes a hardware interface is provided in the first logical partition. A virtual device driver is provided in the second logical partition that provides a set of functions that is at least partially defined by querying the I/O adapter device driver in the first logical partition. The I/O adapter sharing mechanism includes a transfer mechanism that allows data to be transferred directly from the virtual device driver in the second logical partition to the I/O adapter without passing through the I/O adapter device driver in the first logical partition.

Sharing a network I/O adapter between logical partitions

A hosting partition update mechanism allows updating I/O capability of a logically-partitioned computer system in a way that minimally affects the performance and availability of I/O in the computer system. When an update is needed, a new hosting partition is created with the desired update(s). I/O adapters in the current hosting partition are then migrated to the new hosting partition. The migration of an I/O adapter from the current hosting partition to the new hosting partition is relatively fast, thereby minimally impacting system performance and availability of I/O. Once all of the I/O adapters have been migrated to the new hosting partition, the current hosting partition may be kept as a backup, or may be eliminated. Providing a new or backup hosting partition allows updates to be performed in the new or backup hosting partition in a non-disruptive manner while the current hosting partition continues to service I/O requests.

Updating I/O capability of a logically-partitioned computer system

A system, method, and computer-readable medium for detecting errors on a network. According to a preferred embodiment of the present invention, a network error manager retrieves a network topology from a master subnet manager, wherein the network includes a collection of devices coupled by a first interconnect type. When a connectivity failure is detected in the first interconnect type, the network error manager receives from the master subnet manager at least one event notification via a second interconnect type. An error log analysis component identifies at least one device among the collection of devices as a possible cause of the connectivity failure in the first interconnect type. The network error manager retrieves events from at least one device among the collection of devices that can influence a state of the first interconnect type.

Implementing an error log analysis model to facilitate faster problem isolation and repair

At least one input/output (I/O) firmware partition is provided in a partitioned environment to facilitate access to I/O resources owned by the at least one I/O firmware partition. The I/O resources of an I/O firmware partition are shared by one or more other partitions of the environment, referred to as consumer partitions. The consumer partitions use the I/O firmware partition to access the I/O resources. Since the I/O firmware partitions are responsible for providing access to the I/O resources owned by those partitions, the consumer partitions are relieved of this task, reducing complexity and costs in the consumer partitions.

Facilitating access to input/output resources via an I/O partition shared by multiple consumer partitions

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Austin, TX, United States of America

Chetan Mehta