Netlogic Microsystems, Inc

Mediatek Singapore Pte. Ltd.

Broadcom Corporation

Mediatek Corporation

Chetan Deshpande

Sandeep Khanna

Gajanan Sahebrao Jedhe

Varadarajan Srinivasan

Bindiganavale S Nataraj

Gaurang Prabhakar Narvekar

Maheshwaran Srinivasan

Vinay Iyengar

Ritesh Garg

Greg Watson

Carl Gyllenhammer

De Cai Li

Venkat Gaddam

Cheng-Xin Xue

Venkat Rajendher Reddy Gaddam

Sushil Kumar

Zijie Guo

Yi-Wei Chen

John Zimmer

A compute-in-memory (CIM) device includes a memory cell and calculation circuitry configured to perform a calculation based on an input value and a value stored in the memory cell, and to provide a signal at an output node based on the calculation. The CIM device also includes write circuitry configured to perform a write operation on the memory cell and precharge circuitry configured to precharge the output node in response to the write circuitry performing the write operation.

Reducing precharge current surge in digital compute in memory

Aspects of the present disclosure are directed to devices and methods for performing MAC operations using a TCAM array as a compute-in-memory (CIM) device that can enable higher computational throughput, higher performance and lower energy consumption compared to computation using a processor outside of a memory array. In some embodiments, weights in a weight matrix may be programmed in SRAMs of a TCAM bit cell array. Each SRAM may operate as a multiplier that performs a multiplication between the stored weight to an input activation value applied at a search line in the TCAM bit cell array. The two SRAMs within a TCAM bit cell may operate independently to receive independently two input activation values on their respective select lines, and to perform a multiplication operation with the stored weight in each respective SRAM.

Method and apparatus for performing a MAC operation in a memory array

An output node of a cell of a memory device is precharged based on an activation input for the cell. A memory device includes precharge circuitry configured to precharge an output node of a cell of the memory device based on an activation input for the cell.

Reducing precharge power consumption in a memory array

Aspects of the present disclosure are directed to devices and methods for performing MAC operations using a memory array as a compute-in-memory (CIM) device that can enable higher computational throughput, higher performance and lower energy consumption compared to computation using a processor outside of a memory array. In some embodiments, an activation architecture is provided using a bit cell array arranged in rows and columns to store charges that represent a weight value in a weight matrix. A read word line (RWL) may be repurposed to provide the input activation value to bit cells within a row of bit cells, while a read-bit line (RBL) is configured to receive multiplication products from bit cells arranged in a column. Some embodiments provide multiple sub-arrays or tiles of bit cell arrays.

Memory array with programmable number of filters

A content addressable memory (CAM) device includes multiple CAM sub-banks Each CAM sub-bank includes an array of CAM cells arranged in rows and columns and partitioned into a first stage and a second stage along a column dimension. Each CAM sub-bank further includes first-stage match lines (MLs), first-stage search line (SL) pairs, second-stage MLs, and second-stage SL pairs. Each second-stage SL pair is coupled to a column of CAM cells in the second stage and is gated by an SL enable (SL_EN signal). Each CAM sub-bank further includes a circuit operative to receive all of the first-stage MLs as input and de-assert the SL_EN signal when none of the first-stage MLs indicate a match. De-assertion of the SL_EN signal blocks a second portion search key from being provided to the second-stage SL pairs.

Dynamically gated search lines for low-power multi-stage content addressable memory

Ternary content-addressable memory (TCAM) devices are described. The TCAMs described herein are designed to perform write operations—including data writes and mask writes—in a single clock cycle. For example, data input is written in a row of the TCAM during the first portion of a clock cycle, and a mask is written in another row of the TCAM during the second portion of the clock cycle, for example immediately after or after a programmable delay from the data write. In one implementation, a first bus is used both for data write and key search operations, and a second bus is used both for mask write and search masking operations. In another implementation, a first bus is used both for data write and key search operations, a second bus is used for mask write operations, and a third bus is used for search masking operations.

Methods for writing ternary content addressable memory devices

A ternary content addressable memory (TCAM) device comprising an input interface having a first input for receiving first data and a second input for receiving second data; and a memory configured to write the first data into an address selected row of the memory at the same time that a comparison is performed between the second data and at least one other row of the memory different from the address selected row. More particularly, the input interface may further have a third input for receiving a search enable signal and a fourth input for receiving a write enable signal, wherein the memory is configured to write the first data and perform the comparison in response to assertion of the search enable signal at the same time as assertion of the write enable signal. An associated method is also provided.

Simultaneous write and search operation in a content addressable memory

Ternary content-addressable memory (TCAM) devices are described. The TCAMs described herein are designed to perform write operations&#x2014;including data writes and mask writes&#x2014;in a single clock cycle. For example, data input is written in a row of the TCAM during the first portion of a clock cycle, and a mask is written in another row of the TCAM during the second portion of the clock cycle. In one implementation, a first bus is used both for data write and key search operations, and a second bus is used both for mask write and search masking operations. In another implementation, a first bus is used both for data write and key search operations, a second bus is used for mask write operations, and a third bus is used for search masking operations.

Multi-stage content addressable memory devices are described. Some embodiments relate to memory devices including a plurality of rows of memory cells, multiple match lines and multiple pre-charge circuits. A first row of the plurality of rows includes a first segment and a second segment. The first segment may include a first subset of the memory cells of the first row and the second segment may include a second subset of the memory cells of the first row. The first match line is coupled to the memory cells of the first subset, and the second match line is coupled to the memory cells of the second subset. The first pre-charge circuit is configured to pre-charge the first match line to a first pre-charge voltage, and the second pre-charge circuit is configured to pre-charge the second match line to a second pre-charge voltage different from (e.g., greater than) the first pre-charge voltage.

Low-power multi-stage/multi-segment content addressable memory device

Separate key processing units generate different search keys based off of a single master key received at a ternary memory array chip. A reference search key and selection logic are provided to reduce power dissipation in a global search key bus across the chip. The reference search key is the output of one of the key processing units and its bytes are compared with the output from each of the other key processing units. A select signal from each unit indicates which bytes match. Each matching byte at each key processing unit is blocked from changing corresponding bit line logic values across the chip, reducing the number of voltage switches occurring in the global search key bus. The select signal causes a selection module local to each superblock to select the matching byte(s) from the reference search key and non-matching byte(s) from the global search key bus to reconstitute the entire search key.

Apparatus and method for distributing a search key in a ternary memory array

A CAM device including a CAM array, multiple match resolution (MMR) circuitry, and a priority encoder allows the addresses of multiple matching locations resulting from a first search operation to be generated without losing the match results generated in second search operation initiated prior to detection of the multiple match condition for the first search operation. When the multiple match condition is detected, the MMR circuitry asserts a stall signal that stalls search operations in the CAM array. The asserted stall signal also causes the match results of the first and second search operations to be stored in separate memory elements so that the addresses of all matching locations for the first search operation can be generated without disturbing the match results of the second search operation.

Multiple match detection for multiple flows in a content addressable memory

An integrated circuit device for delivering power to a load includes a controller circuit, a cascade circuit, and a power delivery circuit. The controller circuit generates a plurality of control signals. The cascade circuit receives the control signals from the controller circuit and sequentially outputs the control signals onto a cascade bus. The power delivery circuit receives the control signals from the controller circuit and delivers an amount of current to the load, in response to one of the control signals.

Multi-phase power system with redundancy

A shared stack dual-phase CAM cell is provided. The CAM cell includes at least first and second stacks that share a single pair of pull-down transistors. At least one pair of pull-down transistors can thus be eliminated, reducing the area and power consumption of the CAM cell. Sharing of the single pair of pull-down transistors is enabled by time-staggered pre-charge and compare operations such that the pre-charge interval of the first stack corresponds to the compare interval of the second stack, and vice versa.

Shared stack dual phase content addressable memory (CAM) cell

A CAM device is disclosed that includes an array of CAM cells in which the compare circuits of groups of CAM cells are connected together using a conductive layer interposed between a polysilicon layer of the CAM device and the metal-layer of the CAM device. This allows the data lines (e.g., the bit lines and/or comparand lines) of the CAM array to be formed in the metal-layer of the CAM device, which in turn allows the match lines of the CAM array to be formed in the metal-layer of the CAM device. The conductive layer, which may be a silicide layer, is connected to the match line by a via extending from the conductive layer through the metal-layer to the metal-layer.

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San Jose, CA, United States of America

Chetan Deshpande