Kla Corporation

Chet V Lenox

David W Price

Oreste Donzella

Robert J Rathert

John Charles Robinson

Kara L Sherman

Justin Lach

Shifang Li

Stilian Pandev

Mike Von Den Hoff

Barry Saville

Robert Cappel

Thomas Groos

A die screening system may receive die-resolved metrology data for a population of dies on one or more samples from the one or more in-line metrology tools after one or more fabrication steps, where the die-resolved metrology data includes images generated using one or more measurement configurations of the one or more in-line metrology tools. In this way, the die-resolved metrology data provides many measurement channels per die, where a particular measurement channel includes data from a particular pixel of a particular image. The controller may then generate screening data for the population of dies from the die-resolved metrology data, where the screening data includes a subset of the plurality of measurement channels of the die-resolved metrology data, and screen the plurality of dies into two or more disposition classes including at least outlier dies based on variability in the screening data.

Imaging reflectometry for inline screening

Systems and methods for determining a diagnosis of a screening system are disclosed. Such systems and methods include identifying defect results based on inline characterization tool data, identifying electrical test results based on electrical test data, generating one or more correlation metrics based on the defect results and the electrical test results, and determining at least one diagnosis of the screening system based on the one or more correlation metrics, the diagnosis corresponding to a performance of the screening system.

System for automatic diagnostics and monitoring of semiconductor defect die screening performance through overlay of defect and electrical test data

Systems and methods for generating defect criticality are disclosed. Such systems and methods may include identifying defect results including a defect and a defect location. Such systems and methods may include receiving fault test recipes configured to test potential faults at a plurality of testing locations. Such systems and methods may include identifying a plurality of N-detect parameters based on a countable number of times the fault test recipes are configured to test a potential fault. Such systems and methods may include determining a plurality of weighting parameters based on the plurality of N-detect parameters. Such systems and methods may include generating the defect criticality for the defect based on a proximity between the plurality of testing locations and the defect location and the plurality of weighting.

System and method to weight defects with co-located modeled faults

Systems and methods for semiconductor adaptive testing using inline defect part average testing are configured to receive a plurality of inline defect part average testing (I-PAT) scores from an I-PAT system, where the plurality of I-PAT scores is generated by the I-PAT system based on semiconductor die data for a plurality of semiconductor dies, where the semiconductor die data includes characterization measurements for the plurality of semiconductor dies, where each I-PAT score of the plurality of I-PAT scores represents a weighted defectivity determined by the I-PAT system based on a characterization measurement of a corresponding semiconductor die of the plurality of semiconductor dies; apply one or more rules to the plurality of I-PAT scores during a dynamic decision-making process; and generate one or more adaptive tests for at least one semiconductor die of the plurality of semiconductor dies based on the dynamic decision-making process.

Systems and methods for semiconductor adaptive testing using inline defect part average testing

A system and method for identifying latent reliability defects (LRD) in semiconductor devices are configured to perform one or more stress tests with one or more stress test tools on at least some of a plurality of wafers received from one or more in-line sample analysis tools to determine a passing set of the plurality of wafers and a failing set of the plurality of wafers, perform a reliability hit-back analysis on at least some of the failing set of the plurality of wafers, analyze the reliability hit-back analysis to determine one or more geographic locations of one or more die fail chains caused by one or more latent reliability defects (LRD), and perform a geographic hit-back analysis on the one or more geographic locations of the one or more die fail chains caused by the LRD.

System and method for identifying latent reliability defects in semiconductor devices

A system and method for evaluating the reliability of semiconductor die packages are configured to sort a plurality of semiconductor dies with a Known Good Die (KGD) subsystem based on a comparison of an inline part average testing (I-PAT) score of each of the plurality of semiconductor dies to a plurality of I-PAT score thresholds, where the semiconductor die data includes the I-PAT score for each of the plurality of semiconductor dies, where the I-PAT score represents a weighted defectivity of the corresponding semiconductor die. The semiconductor dies may be filtered to remove at-risk semiconductor dies prior to sorting. The semiconductor die data may be received from a plurality of semiconductor die supplier subsystems. The KGD subsystem may transmit semiconductor die reliability data about the sorted plurality of semiconductor dies to a plurality of semiconductor die packager subsystems.

Systems and methods for evaluating the reliability of semiconductor die packages

Systems and methods for semiconductor defect-guided burn-in and system level tests (SLT) are configured to receive a plurality of inline defect part average testing (I-PAT) scores from an inline defect part average testing (I-PAT) subsystem, where the plurality of I-PAT scores is generated by the I-PAT subsystem based on semiconductor die data for a plurality of semiconductor dies, where the semiconductor die data includes characterization measurements for the plurality of semiconductor dies, where each I-PAT score of the plurality of I-PAT scores represents a defectivity determined by the I-PAT subsystem based on a characterization measurement of a corresponding semiconductor die of the plurality of semiconductor dies; apply one or more rules to the plurality of I-PAT scores during a dynamic decision-making process; and generate one or more defect-guided dispositions for at least one semiconductor die of the plurality of semiconductor dies based on the dynamic decision-making process.

Systems and methods for semiconductor defect-guided burn-in and system level tests

A system and method for Z-PAT defect-guided statistical outlier detection of semiconductor reliability failures includes receiving electrical test bin data with semiconductor die data for a plurality of wafers in a lot generated by a statistical outlier detection subsystem configured to perform Z-direction Part Average Testing (Z-PAT) on test data generated by an electrical test subsystem after fabrication of the plurality of wafers in the lot, receiving characterization data for the plurality of wafers in the lot generated by a semiconductor fab characterization subsystem during the fabrication of the plurality of wafers in the lot, determining a statistical correlation between the electrical test bin data and the characterization data at a same x, y position on each of the plurality of wafers in the lot, and locating defect data signatures on the plurality of wafers in the lot based on the statistical correlation.

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Lexington, TX, United States of America

Chet V Lenox