Micron Technology Incorporated

Chet E Carter

Collin Howder

Justin B Dorhout

Kunal R Parekh

Martin Ceredig Roberts

Matthew Park

David A Daycock

Mohd Kamran Akhtar

Justin D Shepherdson

Vinayak Shamanna

Ryan L Meyer

John David Hopkins

Andrey V Zagrebelny

Indra V Chary

Scott E Sills

Eugene P Marsh

Timothy A Quick

Stefan Uhlenbrock

Kunal Shrotri

Fei Wang

Ian C Laboriante

Jordan D Greenlee

Paolo Tessariol

John Mark Meldrim

Richard J Hill

Everett Allen McTeer

Nancy M Lomeli

Joseph Neil Greeley

Erik R Byers

Changhan Kim

Jie Li

Andrew D Carswell

Yifen Liu

Cole Smith

George Matamis

Anilkumar Chandolu

Matthew J King

Alyssa N Scarbrough

Brett D Lowe

Tecla Ghilardi

Jun Fang

Ryan M Meyer

Andrew Li

Haoyu Li

Grady S Waldo

M Jared Barclay

Joshua Wolanyk

Bhavesh Bhartia

Some embodiments include a method of forming an assembly (e.g., a memory array). A first opening is formed through a stack of alternating first and second levels. The first levels contain silicon nitride, and the second levels contain silicon dioxide. Some of the silicon dioxide of the second levels is replaced with memory cell structures. The memory cell structures include charge-storage regions adjacent charge-blocking regions. Tunneling material is formed within the first opening, and channel material is formed adjacent the tunneling material. A second opening is formed through the stack. The second opening extends through remaining portions of the silicon dioxide, and through the silicon nitride. The remaining portions of the silicon dioxide are removed to form cavities. Conductive regions are formed within the cavities. The silicon nitride is removed to form voids between the conductive regions. Some embodiments include memory arrays.

Memory arrays, and methods of forming memory arrays

Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies and methods of forming integrated assemblies

Integrated circuitry comprising a memory array comprises strings of memory cells comprising laterally-spaced memory blocks individually comprising a first vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier. The conductive tiers individually comprise a horizontally-elongated conductive line. A second vertical stack is aside the first vertical stack. The second vertical stack comprises an upper portion and a lower portion. The upper portion comprises vertically-alternating first insulating tiers and second insulating tiers that are of different insulative compositions relative one another. The lower portion comprises a horizontal line above the conductor tier that runs parallel with the laterally-spaced memory blocks in the first vertical stack. Other embodiments, including method, are disclosed.

Integrated circuitry comprising a memory array comprising strings of memory cells and method used in forming a memory array comprising strings of memory cells

A method used in forming a memory array comprises forming a substrate comprising a conductor tier comprising an upper conductor material and a lower conductor material, and a stack comprising vertically-alternating first tiers and second tiers above the conductor tier. Horizontally-elongated trenches are formed through the stack to the upper conductor material and the lower conductor material. At least one of the upper and lower conductor materials have an exposed catalytic surface in the trenches. Metal material is electrolessly deposited onto the catalytic surface to cover the upper conductor material and the lower conductor material within the trenches. Channel-material strings of memory cells are formed and extend through the second tiers and the first tiers. Other embodiments, including structure independent of method, are disclosed.

Memory arrays and methods used in forming a memory array comprising strings of memory cells

A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.

Memory devices including different tier pitches, and related electronic systems

A microelectronic device may include a source structure and a stack structure. The stack structure may include a vertically alternating sequence of insulative structures and conductive structures. Filled slits may extend through the stack structure and into the source structure, the slits dividing the stack structure into multiple blocks. Memory cell pillars may extend through the stack structure and into the source structure, the memory cell pillars and the filled slits terminated at substantially the same depth within the source structure as one another.

Methods of forming microelectronic devices

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier by conducting material that is in a lowest of the conductive tiers and that is directly against multiple of the channel-material strings. A through-array-via (TAV) region comprises TAVs that individually extend through the lowest conductive tier and into the conductor tier. Individual of the TAVs in the lowest conductive tier comprise a conductive core having an annulus circumferentially there-about. The annulus has dopant therein at a total dopant concentration of 0.01 to 30 atomic percent. Insulative material in the lowest conductive tier is circumferentially about the annulus and between immediately-adjacent of the TAVs. Other embodiments, including method, are disclosed.

Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells

Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.

Integrated structures including material containing silicon, nitrogen, and at least one of carbon, oxygen, boron and phosphorus

A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers above a substrate. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Catalytic material is formed in a bottom region of individual of the trenches. Metal material is electrolessly deposited onto a catalytic surface of the catalytic material to individually fill at least a majority of remaining volume of the individual trenches. Channel-material strings are formed and extend through the first tiers and the second tiers. Other embodiments, including structure independent of method, are disclosed.

Microelectronic devices including varying tier pitch, and related electronic systems

Microelectronic devices including filled slits and memory cell pillars, and related memory devices and electronic systems

A method used in forming a memory array and conductive through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. A mask is formed comprising horizontally-elongated trench openings and operative TAV openings above the stack. Etching is conducted of unmasked portions of the stack through the trench and operative TAV openings in the mask to form horizontally-elongated trench openings in the stack and to form operative TAV openings in the stack. Conductive material is formed in the operative TAV openings in the stack to form individual operative TAVs in individual of the operative TAV openings in the stack. A wordline-intervening structure is formed in individual of the trench openings in the stack.

Memory arrays and methods used in forming a memory array and conductive through-array-vias (TAVs)

Growing community of inventors

Boise, ID, United States of America

Chet E Carter