Silicon Laboratories Inc.

Chester Yu

Tiago Marques

Kenneth Wilson Fernald

Brian Taylor Brunn

Vitor Pereira

Guner Arslan

Paul Zavalney

Adrianus Josephus Bink

Hegong Wei

Mehmood Ur Rehman Awan

Y Hao Lim

A Viterbi Equalizer having a limited number of stages is disclosed. In some embodiments, the Viterbi Equalizer may have only four stages. The Viterbi Equalizer produces soft decisions, which comprise a final decision and reliability information related to that final decision. The Viterbi Equalizer is able to provide reliability information even if all paths do not converge on the final decision at the last stage. The reliability information is calculated based on if and when the paths in the trellis converge on a final decision. This reliability information can be used downstream, such as by another Viterbi Algorithm block to perform forward error correction. The use of soft decision provides gains of up to several dB in performance. Additionally, the Viterbi Equalizer is low cost and readily implemented in hardware or software.

Viterbi equalizer with soft decisions

Improved clock gating cells and related methods are provided. The clock gating cells include a first mutually exclusive element (ME), a first inverter and a second mutually exclusive element (ME). MEreceives a clock input and an enable signal, which is asynchronous to the clock input, and outputs the enable signal based on a timing relationship between the clock input and the enable signal. The first inverter receives the enable signal output from MEand provides an inverted enable signal to ME. MEreceives the clock input and the inverted enable signal, and provides a clock output based on a timing relationship between the clock input and the inverted enable signal. Together, MEand MEresolve meta-stability and eliminate glitches in the clock output by preventing rising and falling edges of the enable signal from passing through the mutually exclusive elements during active phases of the clock input.

Asynchronous clock gating cells and related methods to provide a gated clock output

An integrated circuit includes a clock management unit that selectively provides a clock signal, an energy management circuit that provides an internal power supply voltage to an internal voltage rail in response to an external power supply voltage, and has a capacitor coupled between the internal voltage rail and a reference voltage terminal, and a clocked digital circuit that is coupled to the internal voltage rail and the reference voltage terminal and operates in synchronism with the clock signal. The clock management unit provides the clock signal at a first frequency during a standby state, continuously at a second frequency higher than the first frequency during an active state, and during a first clock cycle following an end of the standby state while suppressing the clock signal during at least one subsequent clock cycle during a transition state between the standby state and the active state.

Integrated circuit clock management during low power operations

An oscillation circuit including a crystal interface, a crystal amplifier, a level detector, a timing circuit, and a controller. When activated, the crystal amplifier drives a crystal coupled to the crystal interface to establish oscillation, and the level detector indicates when a target amplitude is detected. The controller activates the crystal amplifier and uses the timing circuit and the level detector to measure a startup time of oscillation. The measured startup time is used in calculating a wake up time from a sleep mode in time to perform an operation at a scheduled time. The startup time may be adjusted or averaged and may be remeasured with temperature change. A method of minimizing startup time of a crystal oscillator includes measuring startup time for determining a delay value for programming a wakeup circuit. Robust startup settings may be used in the event of startup failure due to a sleepy crystal.

Crystal oscillator startup time optimization

An oscillation circuit including a crystal interface for coupling to a crystal, a crystal amplifier that drives the crystal to establish oscillation, a memory, a timing circuit, a level detector that provides an amplitude indication when an oscillation achieves a programmable threshold, and a controller. The controller applies one or more settings including gain and activates the crystal amplifier, measures the startup time, and calculates startup energy. The startup energy is based on a bias current of the crystal amplifier, remaining system current, and the startup time. The settings may include a gain setting of the crystal amplifier and one or more thresholds used by the threshold detector. The controller adjusts the settings for multiple startups, and determines optimal settings for minimizing the startup energy. The memory stores the optimal settings along with robust settings that may be used on a one-time basis in the event of startup failure.

Crystal oscillator adaptive startup energy minimization

A signal gating circuit includes a logic circuit that receives a stop signal and an input signal and provides an intermediate signal in response, and a pulse stretcher. The pulse stretcher provides an output signal with no pulse when a width of a pulse of the intermediate signal is less than a first amount, with a pulse having a first pulse width that begins after a start of the pulse of the intermediate signal and ends at a predetermined delay thereafter when a pulse width of the intermediate signal is greater than the first amount but less than a second amount, and with a pulse having a second pulse width that begins after the start of the pulse of the intermediate signal and ends after an end of the pulse of the intermediate signal when a pulse width of the intermediate signal is greater than the second amount.

Growing community of inventors

Austin, TX, United States of America

Chester Yu