Digital Equipment Corporation

Compaq Computer Corporation, Inc.

Chester W Pawlowski

Nicholas A Warchol

Simon C Steely, Jr

Stephen R Van Doren

David Gerard Conroy

Kourosh Gharachorloo

R Stephen Polzin

Nitin Dhiroobhai Godiwala

Madhumitra Sharma

Andrew Myer Ebert

An improved I/O processor (IOP) delivers high I/O performance while maintaining inter-reference ordering among memory reference operations issued by an I/O device as specified by a consistency model in a shared memory multiprocessor system. The IOP comprises a retire controller which imposes inter-reference ordering among the operations based on receipt of a commit signal for each operation, wherein the commit signal for a memory reference operation indicates the apparent completion of the operation rather than actual completion of the operation. In addition, the IOP comprises a prefetch controller coupled to an I/O cache for prefetching data into cache without any ordering constraints (or out-of-order). The ordered retirement functions of the IOP are separated from its prefetching operations, which enables the latter operations to be performed in an arbitrary manner so as to improve the overall performance of the system.

Method and apparatus for employing commit-signals and prefetching to

A method and apparatus for determining when an Input/Output (I/O) module should prefetch cache lines of data from main memory. Following a request for data from a peripheral, connected to an I/O bus which supports a flexible protocol allowing peripherals with various capabilities to operate, the I/O module will request a cache line of data from main memory containing a beginning portion of the requested data. The I/O module may then prefetch consecutive cache lines containing requested data according to the operating parameters of the peripheral requesting the data and the requested data. The I/O module may prefetch in such way that neither system bus bandwidth nor I/O bus bandwidth is wasted.

Controlled prefetching of data requested by a peripheral

An electronic testing system can test an electronic device which has more signal pins or pads (i.e., contacts) than the maximum number of tester probes. The testing system connects the contacts to the tester such that groups of contacts share individual tester signal lines. The testing system uses special selector logic on the device to be tested to determine which particular contacts of the groups are 'currently output active', or capable of transmitting data. At each step in the testing procedure, the system can vary the sets of contacts which are chosen to be currently output active, thereby resulting in a high percentage of the possible states of the device being tested.

Test methodology for exceeding tester pin count for an asic device

An apparatus including a system bus coupled to an I/O interface which includes a pointer register and a rejecting circuit which determines whether a write to the pointer register will be accepted or rejected. The I/O interface is further coupled to at least one I/O bus having at least one I/O device connected thereto. The system bus is further coupled to a main memory and to a Central Processing Unit (CPU) which is capable of executing software instructions, providing a command structure corresponding to an access of an I/O device, and writing to the pointer register an address of a location in main memory of the command structure. The CPU further includes a hardware indicator responsive to the rejecting circuit for providing a status signal indicating the status of a write to the pointer register. The CPU executes the software in accordance with the status signal. The apparatus allows the software being executed by the CPU to software pend accesses to devices not directly connected to the system bus. This improves system performance over non-pended system buses and reduces the amount of hardware needed as compared to pended system buses.

System for checking the acceptance of I/O request to an interface using

The invention provides a new process and apparatus for generating and selectively processing command requests issued over a bus. Command requests are generated by devices, each of which may be authorized or not authorized to cause the execution of the requested command. A unique identifier is provided for each device. The command requests are received and the identity of the device which issued the command request is determined. The command is then executed only if the unique identifier associated with the requesting device indicates that the device is authorized to cause the execution of the requested command.

Mechanism for screening commands issued over a communications bus for

An apparatus which provides a high data transfer rate to and from an asynchronous bus. The apparatus includes a synchronous logic network to provide a transaction connection between the asynchronous bus and the data transfer device during an initial phase of the transaction when many determinations are required and an asynchronous logic network to provide data transfer between the asynchronous bus and the data transfer device during a subsequent phase of the transaction when very few determinations are required.

Synchronous/asynchronous partitioning of an asynchronous bus interface

A method and apparatus is provided for use in an asynchronous bus interface capable of multiple or single width transfers and controlled by handshake signals, in which the bus transaction may include multiple successive data transfers delineated by a data strobe, and in which each data transfer is terminated by a data handshake signal, and in which data transfers for different cycle types incur different propagation delays, including bus buffering apparatus for directing transfers over single and multiple width busses, and an asynchronous bus controller for returning data handshake signals with individualized timing characteristics in response to the master data strobe and the cycle type of the transaction, such that each successive data transfer is completed in the minimum time that propagation delays, as indicated by the cycle type, will allow, in order to maximize bus throughput.

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North Chelmsford, MA, United States of America

Chester W Pawlowski