International Business Machines Corporation

Infineon Technologies Ag

Chester T Dziobkowski

Sunfei Fang

Cyril Cabral, Jr

Clement Hsingjen Wann

Lawrence Alfred Clevenger

Christian Lavoie

Darryl D Restaino

Timothy Joseph Dalton

Yun-Yu Wang

Chih-Chao Yang

John J Ellis-Monaghan

Zhijiong Luo

Thomas M Shaw

James Spiros Nakos

James J Demarest

Michael Wayne Lane

An L Steegen

Philip L Flaitz

Stefanie Ruth Chiras

James R Lloyd

Ghavam G Shahidi

Vijay Narayanan

Evgeni Petrovich Gousev

Vamsi Krishna Paruchuri

Rajarao Jammy

Derren Neylon Dunn

Michelle Leigh Steen

Patrick William Dehaven

Thomas H Ivers

Keith Kwong Hon Wong

Sampath Purushothaman

Stephen McConnell Gates

John Anthony Fitzsimmons

Terry Allen Spooner

Richard Anthony Conti

Emily R Kinser

Paul Charles Jamison

Kwong Hon Wong

Nivo Rovedo

Paul David Agnello

Ashima B Chakravarti

Stephan Alan Cohen

Horatio Seymour Wildman

Thomas F Houghton

Richard J Murphy

Edward Paul Barth

Tsong-Lin Tai

Carl Emil Bohnenkamp

Frank V Liucci

Hsiang-Jen Huang

Darren N Dunn

Chin-Chao Yang

A method of forming a TEOS oxide layer over an nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide layer formed on a substrate. The method includes forming the nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide layer on a top surface and a top side beveled edge proximate to the top surface of a substrate; removing or preventing formation of a carbon-rich layer on a bottom side bevel edge region proximate to a bottom surface of the substrate or converting the carbon-rich layer to nitrogen doped silicon carbide or nitrogen doped hydrogenated silicon carbide; and forming the TEOS oxide layer on the top surface, the top side beveled edge and the bottom side bevel edge region of the substrate.

Method for preventing backside defects in dielectric layers formed on semiconductor substrates

An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiO&#x2014; or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

Structure to improve adhesion between top CVD low-K dielectric and dielectric capping layer

An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of forming the advanced gate structure is also provided in which the silicided source and drain regions are formed prior to formation of the silicided metal gate region.

Formation of fully silicided metal gate using dual self-aligned silicide process

An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiO- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer

A novel interlevel contact via structure having low contact resistance and improved reliability, and method of forming the contact via. The method comprises steps of: etching an opening through an interlevel dielectric layer to expose an underlying metal (Copper) layer surface; and, performing a low energy ion implant of an inert gas (Nitrogen) into the exposed metal underneath; and, depositing a refractory liner into the walls and bottom via structure which will have a lower contact resistance due to the presence of the proceeding inert gas implantation. Preferably, the inert Nitrogen gas reacts with the underlying exposed Copper metal to form a thin layer of CuN.

Method of forming low resistance and reliable via in inter-level dielectric interconnect

A method of forming a dual self-aligned fully silicided gate in a CMOS device requiring only one lithography level, wherein the method comprises forming a first type semiconductor device having a first well region in a semiconductor substrate, first source/drain silicide areas in the first well region, and a first type gate isolated from the first source/drain silicide areas; forming a second type semiconductor device having a second well region in the semiconductor substrate, second source/drain silicide areas in the second well region, and a second type gate isolated from the second source/drain silicide areas; selectively forming a first metal layer over the second type semiconductor device; performing a first fully silicided (FUSI) gate formation on only the second type gate; depositing a second metal layer over the first and second type semiconductor devices; and performing a second FUSI gate formation on only the first type gate.

Method for forming self-aligned dual fully silicided gates in CMOS devices

A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.

Method for forming self-aligned dual salicide in CMOS technologies

A method of forming a salicide on a semiconductor device includes depositing a first refractory metal layer over a silicon region of a substrate, depositing a near-noble metal layer over the first refractory metal layer, and depositing a second refractory metal layer over the near-noble metal layer. The semiconductor device is annealed in a first annealing process to form a silicide layer abutting the doped region of the semiconductor device. Un-reacted portions of the near-noble metal layer and the second refractory metal layer are removed. The device may be annealed in an optional second annealing process to convert the silicide layer to a low resistance phase silicide material. Junction leakage and bridging are minimized or eliminated by embodiments of the present invention, and a smoother silicided surface is achieved.

Salicide formation method

A diffusion barrier that has a low dielectric constant, k, yet resistant to oxygen and/or moisture permeability is provided. The diffusion barrier includes a dielectric stack having at least two or more dielectric films, each film having a dielectric constant of about 8 or less, wherein the dielectric stack comprises alternating films composed of a high-permeability material and a low-permeability material. A semiconductor structure including substrate having at least one wiring region and the inventive diffusion barrier formed on a surface of the substrate is also provided.

Laminated diffusion barrier

A method of depositing a film on a substrate, comprising placing the substrate in the presence of plasma energy, and contacting the substrate with a reactive gas component comprising a compound of the formula (R&mdash;NH) SiX , wherein R is an alkyl group, n is 1, 2, or 3, and X is selected from hydrogen or the halogens. The reactive gas composition may further comprise an oxidizer and/or a reducing agent.

Methods and materials for depositing films on semiconductor substrates

A charged particle beam apparatus having a cold trap positioned in proximity to components, such as a shaping aperture and a backscattered electrons detector, to which contaminants tend to migrate to adversely affect the functions of these components. As a coolant is passed through the cold trap, the contaminants condense on the cold trap and away from the shaping aperture and the backscattered electrons detector.

Charged particle beam apparatus having anticontamination means

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Hopewell Junction, NY, United States of America

Chester T Dziobkowski