Stratus Technologies Ireland Ltd.

Chester Pawlowski

Andrew Alden

John Chaves

Christopher Cotton

In part, the disclosure relates to a fault tolerant system. The system may include one or more shared memory complexes, each memory complex comprising a group of M computer-readable memory storage devices; one or more cache coherent switches comprising two or more host ports and one or more downstream device ports, the cache coherent switch in electrical communication with the one or more shared memory storage device; a first management processor in electrical communication with the cache coherent switch; a first compute node comprising a first processor and a first cache, the first compute node in electrical communication with the one or more cache coherent switches and the one or more shared memory complexes; a second compute node comprising a second processor and a second cache, the second compute node in electrical communication with the one or more cache coherent switches and the one or more shared memory complexes.

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Burlington, MA, United States of America

Chester Pawlowski