Exponential Technology, Inc.

Cheryl Senter Brashears

James S Blomgren

Earl T Cohen

David E Richter

A processor that can execute both CISC and RISC instructions has an integer pipeline and a floating point pipeline. RISC instructions are sent to the floating point pipeline at the beginning of the integer pipeline, but CISC instructions re-align the floating point pipeline. CISC instructions are sent to the floating point pipeline near the end of the integer pipeline to allow the integer pipeline to fetch memory operands for the floating point pipeline. Thus the floating point pipeline relies on the memory operand fetch facilities of the integer pipeline. Complex CISC fetch-operate instructions pass through the integer pipeline first to fetch a floating point operand, and then begin the floating point pipeline for execution of a floating point operation. However, RISC instructions only use register operands and can begin the floating point pipeline earlier, reducing latency until the floating point result is produced. Rapid re-configuration of the pipeline alignment between a pipeline optimized for RISC instructions and one optimized for CISC instructions is possible with muxes and a mode register. Exception handling and pipeline coordination are also described.

Temporal re-alignment of a floating point pipeline to an integer

A dual-instruction-set central processing unit (CPU) is capable of executing floating point instructions from a reduced instruction set computer (RISC) instruction set and from a complex instruction set computer (CISC) instruction set. Floating point data is transferred from a CISC program to a RISC program running on the CPU by using shared floating point registers. The architecturally-defined floating point registers in the CISC instruction set are merged or folded into some of the architecturally-defined floating point registers in the RISC architecture so that these merged registers are shared by the two instructions sets. In particular, the floating-point exception-mask and flags registers defined by each architecture are merged together so that CISC instructions and RISC instructions implicitly update the same merged flags register when executing floating point instructions. The RISC and CISC registers are folded together so that the CISC flags and RISC flags with the same function are merged to the same register bit. The floating-point data registers are also merged together, allowing a CISC program to pass floating-point data to a RISC program merely by writing one of its floating-point data registers, switching control to the RISC program, and the RISC program reading one of its floating-point data registers that is merged with and corresponds to the CISC floating-point data register that was written to by the CISC program. An extended-precision CISC data format is supported by pairing two of the RISC-size floating-point data registers.

Shared floating-point registers and register port-pairing in a

The sum from a floating point adder is normalized by an initial shift based on a prediction for the position of the leading one or zero in the sum. This leading-one/zero prediction is based not on the operands input to the adder, nor the result from the adder, but on the intermediate generate and propagate signals within the adder. The adder has a first stage that reduces each bit-position to a generate and a propagate signal. The adder's second stage propagates the carries in the adder using these generate and propagate signals to generate the sum. Thus the adder's first-stage logic is also used for the leading one/zero prediction, reducing cost and complexity. An ECL half-adder cell is preferably used for the adder's first stage. A zero output is added to the ECL half-adder cell at minimal cost. The shift for the leading one/zero prediction is accomplished in two stages, with a selective complement of negative sums between the two-stage shift. This allows more time for a more exact prediction after the first coarse shift. The final exact detection of the leading one is pipelined to detect the sum after the complementor but before the second stage of the shifter. This allows the final exact detection of the leading one to occur in parallel with the second stage of the shifter, reducing the delay for generating the final normalized sum by a final shifter.

Inexact leading-one/leading-zero prediction integrated with a

Exponents are first combined together, in a way that varies with the type of floating point operation. A single intermediate exponent result is placed on an intermediate exponent bus. This intermediate exponent is adjusted upwards for any carry-out from the operation on the mantissas, or downwards for any cancellation of leading mantissa bits, producing the final exponent result. The intermediate exponent on the intermediate exponent bus is also compared to a single criteria which is used for all types of floating point operations. Thus the compare logic may be simplified because only a single set of criteria is used for all types of operations. Alternately, the criteria may be varied depending upon the degree of precision used by all operations. Because the intermediate exponent is used, separate exponent adders are not necessary for the prediction unit and the floating point unit. Compound floating point operations may require more complex logic for combining the exponents. The more complex logic is needed to calculate the exponent for the result, so again no additional logic is needed for prediction. Only a single exponent is outputted to the intermediate exponent bus. Thus compound floating point operations may be accommodated simply with the modifications needed for the exponent combination logic.

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Cupertino, CA, United States of America

Cheryl Senter Brashears