Lucent Technologies Inc.

At&t Bell Laboratories

Agere Systems Inc.

Cheryl Anne Bollinger

Sailesh Mansinh Merchant

Pradip Kumar Roy

Kurt George Steiner

Arun Kumar Nanda

Edward Alan Dein

Cletus Walter Wilkins, Jr

Seungmoo Choi

William Thomas Cochran

Stephen Arlon Meisner

Min-Liang Chen

David P Favreau

Daniel Mark Wroge

Daniel J Vitkavage

Gerard Zaneski

Catherine Ann Fieber

A method for manufacturing a semiconductor wafer uses a reticle having a plurality of spaced apart circuit images of identical patterns or images of a common level of a single integrated circuit formed on the reticle and arranged in columns and rows about its central point. At least one column of spaced apart test images are formed outside of and adjacent an outermost column of circuit images. Radiation is projected through the reticle for exposing the patterns on the reticle onto an underlying wafer. A reticle holder having a pair of shutter elements aligned parallel to the columns of images selectively blocks the projection of radiation through the columns of the test images but are exposed in order to form test circuits on the wafer at selected locations.

Multiple purpose reticle layout for selective printing of test circuits

An integrated circuit and its method of formation are disclosed. The circuit utilizes a spin-on glass as an interlevel dielectric. Above and below the spin-on glass is located a phosphorous doped dielectric. The doped dielectric prevents sodium from becoming mobile under the influence of subsequently applied electric fields.

Integrated circuit dielectric formation

A Si IC includes an Al-based layer which is deposited as a composite of sublayers of different composition Al-based materials. In one embodiment a first sublayer comprises an Al-Si-based alloy disposed so as to prevent substantial Si migration into the first sublayer, and a second sublayer, above the first, comprises an Al-based alloy with substantially no Si to alleviate precipitation-induced problems.

Multilayered A1-alloy structure for metal conductors

A Si IC includes an Al-based layer which is deposited as a composite of sublayers of different composition Al-based materials. In one embodiment a first sublayer comprises an Al-Si-based alloy disposed so as to prevent substantial Si migration into the first sublayer, and a second sublayer, above the first, comprises an Al-based alloy with substantially no Si to alleviate precipitation-induced problems. The selection of the thickness of the second sublayer to be a major portion and the inclusion of barrier layers are also described.

Method of making multilayered Al-alloy structure for metal conductors

Self-aligned contacts are formed to regions between closely spaced features by a method which uses differential etch rates between first and second dielectrics deposited over the closely spaced features.

Integrated circuit with planar dielectric layer

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Orlando, FL, United States of America

Cheryl Anne Bollinger