Texas Instruments Corporation

Cherry Lyn Marquez Aranas

Dolores Babaran Milo

Randy Collo Ramos

Mark Daniel Pabalate Minoc

Russel Rosales Borreo

Jeniffer Viera Otero

A semiconductor device includes a silicon die having a metal material coating applied on one side, a lead frame having a mounting pad having an area smaller than an area of the silicon die, the silicon die being mounted on the lead frame via the mounting pad, and an etched area filled with a non-conductive mold compound on a side of the lead frame that comes into contact with an end of the silicon die along an edge of the silicon die. A volume of epoxy material is dispensed onto the lead frame along a length of the metal material coating to form a fillet weld on a side of the silicon die configured to adhere the silicon die to the lead frame and to prevent the metal material coating from coming into contact with the lead frame.

Lead frame for a die

In a described example, a method for making a packaged semiconductor device includes laser ablating a first groove with a first width and a first depth into a mounting surface of a substrate between landing pads. A first pillar bump on an active surface of a semiconductor device is bonded to a first landing pad; and a second pillar bump on the semiconductor device is bonded to a second landing pad. A channel forms with the active surface of the semiconductor device forming a first wall of the channel, the first pillar bump forms a second wall of the channel, the second pillar bump forming a third wall of the channel, and a surface of the first groove forms a fourth wall of the channel. The channel is filled with mold compound and at least a portion of the substrate and the semiconductor device are covered with mold compound.

Semiconductor device package with grooved substrate

A multi-level leadframe including three bonding levels and one exposed level. Each of the three bonding levels and the one exposed level is positioned in a different horizontal plane, with each bonding level providing a bonding site vertically positioned relative to the horizontal plane of the exposed level, with each bonding site coupled to a package lead at the exposed level. Bonding sites located at first and second bonding levels can be located in a common, outer row, along a common, vertical plane, and bonding sites located at a third bonding level can be located in a separate, inner row, along a separate vertical plane. A third level bonding site can be coupled to a first level bonding site with a multiple level electrical lead conductor that vertically spans a second bonding level. A two-step etch process from a single sheet conductor is provided to manufacture the multi-level leadframe.

QFN pin routing thru lead frame etching

A backgrind (BG) tape includes an adhesive material having a thinner tape region with a first thickness having an area sized to accommodate a substrate therein including an active semiconductor top side surface including a plurality of chips each including at least one transistor and at least one metallization level with bond pads connected to nodes of the transistor and bumps on or coupled to the bond pads. The BG tape also includes a thicker tape region along at least a periphery of the BG tape having a second thickness that is greater than the first thickness.

Growing community of inventors

Pampanga, Philippines

Cherry Lyn Marquez Aranas