Taiwan Semiconductor Manufacturing Comp. Ltd.

Chern-yow Hsu

Shih-Chang Liu

Harry-Hak-Lay Chuang

Feng-Jia Shiu

Yu-Hsing Chang

Wei-Chieh Huang

Jieh-Jang Chen

Yao-Wen Chang

Sheng-Huang Huang

Kuei-Hung Shen

Gung-Pei Chang

Ching-sheng Chu

A semiconductor device includes: a first conductive plate and a second conductive plate disposed adjacent to the first conductive plate; a first insulating plate disposed over the first conductive plate and the second conductive plate; a third conductive plate disposed over the first insulating plate; a second insulating plate disposed over the third conductive plate; a fourth conductive plate disposed on one side of the second conductive plate opposite to the first conductive plate; a first conductive spacer disposed on the first insulating plate adjacent to the fourth conductive plate; a first conductive via penetrating the second insulating plate, the first insulating plate, and the first conductive plate, wherein the first conductive via is electrically coupled to the first conductive plate; and a second conductive via penetrating the fourth conductive plate, wherein the second conductive via is electrically coupled to the fourth conductive plate.

Semiconductor device and method of forming the same

A method includes providing a substrate having a conductive column, a dielectric layer over the conductive column, and a plurality of sacrificial blocks over the dielectric layer, the plurality of sacrificial blocks surrounding the conductive column from a top view; depositing a sacrificial layer covering the plurality of sacrificial blocks, the sacrificial layer having a dip directly above the conductive column; depositing a hard mask layer over the sacrificial layer; removing a portion of the hard mask layer from a bottom of the dip; etching the bottom of the dip using the hard mask layer as an etching mask, thereby exposing a top surface of the conductive column; and forming a conductive material inside the dip, the conductive material being in physical contact with the top surface of the conductive column.

Via structure and methods of forming the same

A method for fabricating a semiconductor memory device is provided. The method includes: etching a first region of the semiconductor memory device to expose a first capping layer; forming a second capping layer on the first capping layer; etching a portion of the first capping layer and a portion of the second capping layer to form a first trench reaching a first metal line; and forming a second metal line in the first trench to contact the first metal line.

Semiconductor memory device and method for fabricating the same

The present disclosure provides a semiconductor structure, including an Nmetal layer over a transistor region, where N is a natural number, and a bottom electrode over the Nmetal layer. The bottom electrode comprises a bottom portion having a first width, disposed in a bottom electrode via (BEVA), the first width being measured at a top surface of the BEVA, and an upper portion having a second width, disposed over the bottom portion. The semiconductor structure also includes a magnetic tunneling junction (MTJ) layer having a third width, disposed over the upper portion, a top electrode over the MTJ layer and an (N+1)metal layer over the top electrode. The first width is greater than the third width.

Semiconductor structure and method of forming the same

The present disclosure provides a method for forming a semiconductor structure. The method includes the following operations. A metal layer is formed. An adhesion-enhancing layer is formed over the metal layer. A dielectric stack is formed over the adhesion-enhancing layer. A trench is formed in the dielectric stack. A barrier layer is formed conforming to the sidewall of the trench. A high-k dielectric layer is formed conforming to the barrier layer. A sacrificial layer is formed conforming to the high-k dielectric layer.

Method for forming a semiconductor structure

A semiconductor device includes: a first conductive plate and a second conductive plate disposed adjacent to the first conductive plate; a first insulating plate disposed over the first conductive plate and the second conductive plate; a third conductive plate disposed over the first insulating plate; a second insulating plate disposed over the third conductive plate; a fourth conductive plate disposed over the second insulating plate; a first conductive via penetrating the fourth conductive plate, the second insulating plate, the first insulating plate, and the first conductive plate, wherein the first conductive via is electrically coupled to the fourth conductive plate and the first conductive plate; and a second conductive via penetrating the second insulating plate, the third conductive plate, the first insulating plate, and the second conductive plate, wherein the second conductive via is electrically coupled to the third conductive plate and the second conductive plate.

Growing community of inventors

HSIN-CHU COUNTY, Taiwan

Chern-yow Hsu