Chartered Semiconductor Manufacturing Ltd (corporation)

National University of Singapore

Other

Nanyang Technological University

Institute of Microelectronics

Cher Liang Cha

Lap Chan

Chee Tee Chua

Alex See

Ravishankar Sundaresan

Kheng Chok Tee

Eng Fong Chor

Kok Wai Johnny Chew

Kok Keng Ong

Teck Koon Lee

Subhash Gupta

Yeow Kheng Lim

Wang Ling Goh

Kok Wai Chew

Johnny Kok Wai Chew

Anqing Zhang

Hao Gong

Gong Hao

Shau-Fu Sanford Chu

Zhifeng Joseph Xie

Man Siu Tse

A new method is provided for creating an inductor on the surface of a silicon substrate. The invention provides overlying layers of oxide fins beneath a metal inductor. The oxide fins provide the stability support for the overlying metal inductor while also allowing horizontal air columns to simultaneously exist underneath the inductor. Overlying layers of air cavities that are spatially inserted between the created overlying layers of oxide fins can be created under the invention by repetitive application of the mask used. The presence of the air wells on the surface of the substrate significantly reduces parasitic capacitances and series resistance of the inductor associated with the substrate.

Method to fabricate horizontal air columns underneath metal inductor

The invention provides a new multilevel interconnect structure of air gaps in a layer of IMD. A first layer of dielectric is provided over a surface; the surface contains metal points of contact. Trenches are provided in this first layer of dielectric. The trenches are filled with a first layer of nitride or disposable solid and polished. A second layer of dielectric is deposited over the first layer of dielectric. Trenches are formed in the second layer of dielectric, a second layer of nitride or disposable solid is deposited over the second layer of dielectric. The layer of nitride or disposable solid is polished. A thin layer of oxide is deposited over the surface of the second layer of dielectric. The thin layer of oxide is masked and etched thereby creating openings in this thin layer of oxide, these openings align with the points of intersect of the trenches in the first layer of dielectric and in the second layer of dielectric. The nitride or removable solid is removed from the trenches. The openings in the thin layer of oxide are closed off leaving a network of trenches that are filled with air in the two layers of dielectric that now function as the Inter Level Dielectric.

Method to form a cross network of air gaps within IMD layer

In accordance with the objectives of the invention a new method is provided for creating air gaps in a layer of IMD. First and second layers of dielectric are successively deposited over a surface; the surface contains metal lines running in an Y-direction. Trenches are etched in the first and second layer of dielectric in an X and Y-direction respectively. The trenches are filled with a layer of nitride and polished. A thin layer of oxide is deposited over the surface of the second layer of dielectric. Openings are created through the thin layer of oxide that align with the points of intersect of the nitride in the trenches in the layers of dielectric. The nitride is removed from the trenches by a wet etch, thereby opening trenches in the layers of dielectric with both sets of trenches being interconnected. The openings in the thin layer of oxide are closed, leaving a network of trenches containing air in the two layers of dielectric.

A method for forming shallow trench isolation (STI) with a higher aspect ratio is given. This method allows the formation of narrower and deeper trench isolation regions while avoiding substrate damage due to excessive etching and severe microloading effects. In addition, it yields uniform depth trenches while avoiding problems of etch residue at the bottom of the trench. This method is achieved by using a process where a trench is etched, and an oxide layer grown along the bottom and sidewalls of the trench. Oxygen or field isolation ions are then implanted into the bottom of the trench. A nitride spacer is then formed along the bottom and sidewalls of the trench, followed by an isotropic etch removing the nitride and oxide from the bottom of the trench. An oxide deposition then fills the trench, followed by a planarization step completing the isolation structure.

Effective isolation with high aspect ratio shallow trench isolation and oxygen or field implant

A method of forming shallow junction MOSFETs is achieved. A gate oxide layer is formed overlying a substrate. A first electrode layer, of polysilicon or metal, is deposited. A silicon nitride layer is deposited. The silicon nitride layer and the first electrode layer are etched through to form temporary MOSFET gates. Ions are implanted into the substrate to form lightly doped junctions. A spacer layer is deposited. The spacer layer and the gate oxide layer are anisotropically etched to form sidewall spacers. Ions are implanted into the substrate to form heavily doped junctions. The silicon nitride layer is etched away. A second electrode layer, of polysilicon or metal, is deposited overlying the substrate, the sidewall spacers, and the first polysilicon layer. The second electrode layer is polished down to the top surfaces of the sidewall spacers to complete the MOSFETs and to form permanent gates and conductive connections to the source and drain junctions. The second electrode layer is etched through to form separate conductive connections. An intermetal dielectric layer is deposited. The intermetal dielectric layer is etched through to form contact openings. A metal layer is deposited and etched through to form separate metal interconnects. A passivation layer is deposited, and the integrated circuit is completed.

Method to form shallow junction transistors while eliminating shorts due to junction spiking

Shallow junction transistors which eliminating shorts due to junction spiking

A new method of fabricating a stacked gate Flash EEPROM device having an improved interpoly oxide layer is described. A gate oxide layer is provided on the surface of a substrate. A first polysilicon layer is deposited overlying the gate oxide layer and patterned to form a floating gate. Source and drain regions associated with the floating gate are formed within the substrate. An oxide layer is deposited overlying the floating gate and the substrate. The oxide layer is polished away until the top of the oxide layer is even with the top of the floating gate. A second polysilicon layer is deposited overlying the oxide layer and the first polysilicon layer of the floating gate wherein the second polysilicon layer has a smooth surface. An interpoly dielectric layer is deposited overlying the second polysilicon layer. A third polysilicon layer is deposited overlying the interpoly dielectric layer. The third polysilicon layer and the interpoly dielectric layer are patterned to form a control gate overlying the floating gate. An insulating layer is deposited overlying the oxide layer and the control gate. Contact openings are formed through the insulating layer to the underlying control gate and to the underlying source and drain regions. The contact openings are filled with a conducting layer to complete the fabrication of the Flash EEPROM device.

Flash device having a large planar area ono interpoly dielectric

A method of forming a self-aligned elevated transistor using selective epitaxial growth is described. An oxide layer is provided overlying a semiconductor substrate. The oxide layer is etched through to the semiconductor substrate to form a trench having a lower portion contacting the substrate and an upper portion having a width larger than the width of the lower portion. A silicon layer is grown within the trench using selective epitaxial growth wherein the silicon layer fills the lower portion and partially fills the upper portion. Nitride spacers are formed on the sidewalls of the trench. A polysilicon layer is deposited overlying the oxide layer and within the trench and etched back to form a gate electrode within the trench between the nitride spacers. The nitride spacers are etched away where they are not covered by the gate electrode leaving thin nitride spacers on sidewalls of the gate electrode. Ions are implanted into the silicon layer exposed at the edges of the trench whereby source and drain pockets are formed within the silicon layer wherein the junction depth is determined by the thickness of the silicon layer. A dielectric layer is deposited overlying the oxide layer and the gate electrode and source/drain pockets within the trench to complete formation of the self-aligned elevated transistor in the fabrication of an integrated circuit.

Self-aligned elevated transistor

A method to form robust dual damascene interconnects by decoupling via and connective line trench filling has been achieved. A first dielectric layer is deposited overlying a silicon nitride layer. A shielding layer is deposited. The shielding layer, the first dielectric layer, and the silicon nitride layer are patterned to form via trenches. A first barrier layer is deposited to line the trenches. The via trenches are filled with a first copper layer by a single deposition or by depositing a seed layer and then electroless or electrochemical plating. The first copper layer is polished down to complete the vias. A second barrier layer is deposited. The second barrier layer is patterned to form via caps. A second dielectric layer is deposited. A capping layer is deposited. The capping layer and the second dielectric layer are patterned to form connective line trenches that expose a part of the via caps. A third barrier layer is deposited to line the connective line trenches. The third barrier layer and the via caps are etched to form trench barrier sidewall spacers and to expose the vias. The connective line trenches are filled with a second copper layer by a single deposition, by a first deposition of a seed layer followed by plating, or by plating using the via as the seed layer. The second copper layer is polished down.

Method to form high performance copper damascene interconnects by de-coupling via and metal line filling

Method for forming self-aligned elevated transistor

A method of forming a metal gate structure, on a high k gate insulator layer, for NMOS devices, and simultaneously forming a metal-polysilicon gate structure, on the same high k gate insulator layer, for PMOS devices, has been developed. The method features forming openings in a composite insulator layer, via removal of silicon nitride dummy gate structures that were embedded in a composite insulator layer, with the openings exposing regions of the semiconductor substrate to be used for subsequent NMOS and PMOS channel regions. Deposition of a high k gate insulator layer is followed by deposition of an in situ doped polysilicon layer. After removal of a portion of the in situ doped polysilicon layer located in the NMOS region, a metal layer is deposited on the underlying high k gate insulator layer in the NMOS region, and on the in situ polysilicon layer in the PMOS region. Removal of unwanted regions of metal, and of in situ polysilicon, result in the definition of a metal gate structure, on the high k gate insulator layer, in the NMOS region, and in the definition of a metal&mdash;in situ doped polysilicon gate structure, on the high k gate insulator layer, in the PMOS region, with both gate structures embedded in openings in the composite insulator layer, previously formed via removal of the silicon nitride dummy gate structures.

Method of fabricating CMOS devices featuring dual gate structures and a high dielectric constant gate insulator layer

Formation of a MOSFET with a polysilicon gate electrode embedded within a silicon trench is described. The MOSFET retains all the features of conventional MOSFETs with photolithographically patterned polysilicon gate electrodes, including robust LDD (lightly doped drain) regions formed in along the walls of the trench. Because the gate dielectric is never exposed to plasma etching or aqueous chemical etching, gate dielectric films of under 100 Angstroms may be formed without defects. The problems of over etching, and substrate spiking which are encountered in the manufacture of photolithographically patterned polysilicon gate electrodes do not occur. The entire process utilizes only two photolithographic steps. The first step defines the silicon active area by patterning a field isolation and the second defines a trench within the active area wherein the device is formed. The new process, uses the same total number of photolithographic steps to form the MOSFET device elements as a conventional process but is far more protective of the thin gate oxide.

Embedded polysilicon gate MOSFET

A new method of fabricating an inductor utilizing air as an underlying barrier in the manufacturing of integrated circuits is described. A field oxide region is formed in and on a semiconductor substrate and then removed whereby a well is left in the semiconductor substrate. A polish stop layer is deposited over the substrate and within the well. The polish stop layer is covered and the well filled with a spin-on-glass layer. The spin-on-glass layer is polished back to the polish stop layer. The said polish stop layer is removed. A first oxide layer is deposited overlying the spin-on-glass layer and the semiconductor substrate and is patterned using an inductor reticle whereby a plurality of openings are made through the first oxide layer to the spin-on-glass layer. All of the spin-on-glass layer within the well is removed through the plurality of openings. Thereafter, a second oxide layer is deposited overlying the first oxide layer and capping the plurality of openings thereby forming an air barrier within the well. A metal layer is deposited overlying the second oxide layer and patterned using the same inductor reticle to form the inductor in the fabrication of an integrated circuit device.

Growing community of inventors

Singapore, Singapore

Cher Liang Cha