Hyundai Electronics America, Inc.

Cisco Technology, Inc.

Advanced Array Corp.

Cheow F Yeo

Ray Pinkham

Paul Lazar

Reza Moazeni

Julio C Fuentes

Nishant P Sabadra

Theodore A Carper

The interface devices and platforms described herein provide an M.2 specification interface for multiple types of external devices using a single host connector or socket. The devices determines, from a received voltage level, a device type for an external device connected to a host connector and enables a routing scheme for the plurality of configurable connection paths based on the device type.

Dual interface device with a single M.2 socket

A dynamic random access memory circuit achieves much higher data bandwidth by maximizing the number of memory cell rows that are held open and by indefinitely increasing the time that the rows are open. The boosted voltage of a pump circuit is directed to active rows according to the presence of a pump token. The pump token is present at one location in a circular shift register corresponding to a memory array. The concurrence of the token and a pump-enable signal causes that array to receive a boosted voltage independent of an array-select operation.

Pump control circuit

A memory array includes a plurality of columns, each of said columns including a predetermined number of memory cells. A write driver for generating a signal which facilitates the writing of data to one or more of said memory cells is provided and has coupled to an output terminal thereof a write data line. The write data line, along which signals generated by the write driver propagate to selected memory cells, includes a plurality of column nodes. The columns are divided into groups, where each group contains columns bearing consecutive column addresses. One-half the columns in a first group, which bear the first column addresses, are associated with those column nodes closest to the write driver, while the other half of the columns in the first group, which bear the next consecutive column addresses, are associated with the column nodes furthest from the write driver. One-half the columns in a second group, which bear the next consecutive column addresses, are associated with the next available column nodes closest to the write driver, while the other half of the columns in the second group, which bear the next consecutive column addresses, are associated with the next available column nodes furthest from the write driver.

Apparatus and method for writing to multiple addresses

A method of improving the boosted wordline compliance of a memory circuit. A wordline is grounded prior to boosting with a voltage greater than the circuit bias voltage (e.g. vdd) from a boost voltage generator. Grounding the wordline pulls the gate of a pass transistor to the bias voltage minus a threshold voltage and prepares the pass transistor to self-boost upon boosting the wordline. The transconductance of the pass transistor is improved, improving the charge transfer from the boost generator to the wordline, decreasing rise time. In another embodiment, an isolation transistor between the wordline select circuit and the pass transistor is boosted to provide additional pass transistor gate voltage.

Method of operating a boosted wordline

A video memory device has a normal write mode and a block write mode, and includes a global write driver driving global input/output (I/O) lines, and a number of local write drivers, each driving local I/O lines coupled to a number of memory cells. Control circuitry is coupled to the global write driver and to the local write drivers, and is adapted to generate block write control signals and normal write control signals. The block write control signals cause the write data path to freeze during a block write cycle, thereby conserving power during block writes.

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San Jose, CA, United States of America

Cheow F Yeo