Electronics and Telecommunications Research Institute

Cheon-Soo Kim

Hyun-Kyu Yu

Min Sang Park

Seon-Ho Han

Mun-Yang Park

Nam Hwang

Kee-Soo Nam

Jung-Woo Park

Hyoung-Seok Oh

Song-cheol Hong

Kyu-Ha Baek

Seong-Do Kim

Dong-Woo Kang

Dae-Yong Kim

Bo-Woo Kim

Young-Jae Lee

Sang-Jin Byun

Kwang-Soo Kim

Jang-Hong Choi

Nam Nguyen Hoai

Ki-Su Kim

Hyun-Kyu Yoo

Chung-Hwan Kim

Pil-Jae Park

Baek-Hyun Kim

Sung-Chul Woo

Provided is a power amplifier installed in wireless communication terminals and systems. According to one aspect of the present invention, a reconfigurable power amplifier capable of selecting a wide band frequency is provided. The reconfigurable power amplifier includes input transistors receiving a radio frequency (RF) signal and a reconfigurable adaptive power cell configured to select the wide band frequency by applying a common-gate bias voltage to a plurality of common-gate transistors with a plurality of separate common gates to amplify the RF signal.

Reconfigurable power amplifier capable of selecting wide band frequency and method for selecting wide band frequency

A bandpass filter that provides a wide gain control range is provided. The bandpass filter performs channel filtering and gain control while maintaining the bandpass characteristic of the bandpass filter. The bandpass filter enables gain control for a wide signal amplitude range while maintaining performance characteristics, such as an out-of-band attenuation ratio capable of high linearity and good pass-band flatness.

Bandpass filter providing wide gain control range

A pulse radar apparatus is disclosed. The pulse radar apparatus includes a pulse generation unit, a receiver unit, a synchronization unit, and a switch unit. The pulse generation unit generates a pulse based on a transmission trigger signal having a transmission pulse repetition period, and sends the pulse to a target via a transmission antenna. The synchronization unit generates the transmission trigger signal using an external reference clock, provides the transmission trigger signal to the pulse generation unit, and generates a plurality of clock signals having a time delay with respect to the transmission pulse trigger signal using the external reference clock. The switch unit selects any one clock signal from the plurality of clock signals in response to an external selection signal, and provides the selected clock signal to a receiver unit which utilizes a sampler with provided sampling clocks.

Pulse radar apparatus

Provided is a wireless transceiving apparatus for variability of signal processing band, in which at least one resonator of an analog processor and a VCO are simultaneously controlled using a frequency synthesizer, and a frequency of the VCO and a resonance frequency of the analog processor are controlled to have a rational number ratio, thereby capable of varying the signal processing band. The wireless transceiving apparatus includes: an analog processor having a plurality of resonators on a path of transmission/reception signals, for performing analog signal processing; a digital processor for performing digital signal processing on an output signal of the analog processor or data to be transmitted to the analog processor; and a frequency synthesizer for providing a local oscillation (LO) frequency and a controlling signal to the resonators of the analog processor so as to vary a signal processing band of the analog processor.

Wireless transceiving apparatus for variability of signal processing band

Provided is an apparatus having a variable capacitor circuit which is capable of obtaining a constant gain with respect to a whole control voltage by using a linear variable frequency characteristic for a variation of the control voltages, to thereby attain a wide variable frequency range. For this, a variable capacitor circuit includes a plurality of variable capacitors being connected in parallel with each other and having different capacitances with respect to an input control voltage, wherein the sum of the variable capacitances of the plurality of variable capacitors at a same voltage level of the control voltage varied within the whole control voltage range has linearity.

Variable capacitor circuit having linear capacitance variation and voltage controlled oscillator using the same

Provided is an Inductor-Capacitor (LC) quadrature Voltage Controlled Oscillator (VCO) having a startup circuit which can accurately select one of +90&#xb0; and &#x2212;90&#xb0; as a phase difference between two clocks generated by the LC quadrature VCO by embodying the startup circuit therein by using a phase detector and a controller. The LC quadrature VCO includes a first LC tank for generating a second clock signal and a fourth clock signal, a second LC tank for generating a first clock signal and a third clock signal, a phase detector for receiving the clock signals from the first LC tank and the second LC tank, and detecting whether a phase difference between the clocks is +90&#xb0; or &#x2212;90&#xb0;, and a controller for discriminating whether phase information detected by the phase detector is equivalent to a phase difference between clocks required by the external signal processing unit, and changing an operation mode of the first LC tank and/or the second LC tank on the basis of the discrimination result of the phase difference between the clocks.

LC quadrature VCO having startup circuit

There is provided a transformer for varying an inductance value, which adjusts a tuning range of the inductance without decrease of the inductor's capability by selectively connecting switches to inductors and controls an amount of magnetic flux. And the transformer consists of multiple inductors formed on a semiconductor substrate, which including N number of metal lines, N number of ports made by twisting the metal lines in the form of a symmetric circuit, wherein a certain number of ports among the N number of ports, which are connected to switch elements.

Transformer for varying inductance value

Provided is a power amplifier which fits to a deep-submicron technology in radio frequency wireless communication. The power amplifier includes a cascode including a first transistor which receives and amplifies an input signal, and a second transistor which is connected to the first transistor in series and operated by a DC bias voltage; a third transistor which is connected between the cascode and an output end, operated by a dynamic gate bias and outputting a signal; and a voltage divider which includes first and second capacitors that are connected between the output end, i.e. a drain of the third transistor, and a ground in series, and provides the dynamic bias to a gate of the third transistor.

Triple cascode power amplifier of inner parallel configuration with dynamic gate bias technique

A device structure of a LDMOSFET has trench type sinker formed using a trench process. A semiconductor layer of a first conductive type is formed within the device structure. A field area is formed in a trench structure on one side of the semiconductor layer and a gate electrode is formed on a given surface of the semiconductor layer. A channel layer of a second conductive type is formed by laterally diffusion from the field area to a width containing both sides of the gate electrode. The source area of LDMOS is electrically connected with the substrate through the sinker. By a piercing through the source area, the sinker divides the source area into two source areas. This division reduces the parasitic resistance as well as parasitic capacitance. In addition, the device structure eliminates the need for high temperature diffusion process and reduces lateral diffusion of the sinker.

Device structure of RF LDMOS with trench type sinker

A method of forming an HF power device. The method includes forming a semiconductor layer as a first conductive type on a semiconductor substrate; etching the semiconductor layer forming a first trench; doping an impurity in the neighborhood of the first trench forming a first impurity layer; burying a conduction film into the first trench; etching the semiconductor layer forming a second trench; forming a field oxide film buried into the second trench; forming a gate electrode on a surface of the semiconductor layer; forming a source on the surface of the semiconductor layer; forming a drain area on the surface of the semiconductor layer; forming an LLD area on the surface of the semiconductor layer between the drain area and the gate electrode; forming a first metal electrode; and forming a second metal electrode electrically connected to the LDD area.

Method of making a HF LDMOS structure with a trench type sinker

A method for fabricating an inductor device includes the steps of forming a plurality of trenches in a substrate by selectively etching the substrate, implanting dopants into sidewalls and bottom portion of each trench, forming an oxide layer by oxidizing the trenches and the substrate and simultaneously forming a doped layer in the surroundings of the trenches by diffusing the dopants into the substrate, and forming a dielectric layer on a resultant structure to fill the entrance of the trenches, thereby forming air-gap layers inside the trenches, thereby reducing a parasitic capacitance and a magnetic coupling.

Integrated inductor device and method for fabricating the same

Inductors used for impedance matching in the radio frequency integrated circuits is disclosed. In the integrated inductor device according to the present invention, an additional electrode is arranged in surroundings of an inductor metal line, and the reverse bias voltage is applied to the region between the substrate and the electrode so as to form a depletion layer. Therefore, the substrate biasing is effected and thus an inductor having improved performance can be formed by decreasing the parasitic capacitance between the inductor metal line and the substrate. The present invention can also be applied to another semiconductor device having metal lines and pads.

Inductor devices using substrate biasing technique

An inductor device with a MOS transistor internally installed is disclosed, in which an inductor can be arbitrarily connected in series or in parallel to the respective terminals of MOS transistors by applying a multi-layer wiring technique, thereby reducing the chip area. Within an inductor structure, MOS transistors which have an active region width of W .mu.m are formed in the number of n, and an inductor wire is connected to an arbitrary terminal of the MOS transistors by employing a multi-layer metal wiring process. Thus the inductor is connected to an arbitrary terminal of the MOS transistors in series. Thus an inductor device in which MOS transistors having a channel width of W.times.n .mu.m are internally installed is formed.

MOS transistor embedded inductor device using multi-layer metallization

A method for fabricating a bipolar complementary metal oxide semiconductor device, includes a first step of forming a three-layered substrate of p.sup.- /n.sup.+ /n.sup.- type or n.sup.- /p.sup.+ /p.sup.- type and forming p- and n-wells to be adjacent to each other to the bottom of the top layer of the three-layered substrate; a second step of isolating the p- and n-wells from each other and defining a region for a bipolar transistor on one side to separate base/emitter regions from each other; a third step of defining a gate region to form a metal- oxide semiconductor transistor in each of the p- and n-wells and forming collector/emitter regions in the bipolar transistor region; and a fourth step of forming an n-type metal oxide semiconductor transistor, a p-type metal oxide semiconductor transistor and a bipolar transistor on the p-well, n-well and collector/emitter regions, respectively, and forming source/drain and base electrodes through diffusion by using a doped polycrystalline silicon sidewall spacer.

Growing community of inventors

Daejon, South Korea

Cheon-Soo Kim