Electronics and Telecommunications Research Institute

Korea Telecommunication Authority

Cheon Soo Kim

Hyun Kyu Yu

Ja Yol Lee

Min Sang Park

Mun Yang Park

Seong Do Kim

Dae Youn Kim

Pil Jae Park

Kyu Hwang Lee

Ik Soo Eo

Young Jae Lee

Jin Hyoung Lee

Jang Hong Choi

Minjae Lee

Byung Hun Min

Chung Hwan Kim

Jaehyun Kang

Jin Ho Lee

Jae Young Kim

Hyeong Ho Lee

Young Sun Kim

Tae Il Kim

Dong Woo Kang

Young Ho Kim

Kyung Hwan Park

Min Jae Lee

Bon Tae Koo

Jae Hoon Shim

Dae Yong Kim

Dong-Young Kim

Hee Bum Jung

Seon Ho Han

Sang-Kyun Kim

Chung Kook Lee

Hyun Ho Boo

Sung Kyung Park

Yeong Cheol Hyeon

Jung Woo Park

Jeong-Geun Kim

Min Uk Heo

Myung Shin Kwak

Duong Quoc Hoang

Seon M Hong

Yong B Kim

Go B Choi

Junsoo Ko

Minuk Heo

Provided is a transmitter. The transmitter includes a signal combiner configured to amplify a first differential radio frequency (RF) signal modulated to be transmitted through a first frequency band and a second differential RF signal modulated to be transmitted through a second frequency band non-adjacent to the first frequency band and summate the amplified first differential RF signal and the amplified second differential RF signal in a current mode to generate an RF signal and a power amplifier configured to amplify the generated RF signal.

Transmitter for carrier aggregation

A method and device for calibrating a DC offset and an I-Q imbalance component of an RF transceiver, the method including inputting a test signal into a transmitter, and converting the test signal into an analogue test signal; converting the analogue test signal using a transmitting mixer; sub-sampling a signal output from the transmitting mixer; and computing a DC offset calibrating constant number and an I-Q imbalance calibrating constant number from a sub-sampled signal.

Method and device for calibrating IQ imbalance and DC offset of RF tranceiver

Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal, the PLL including a first phase interpolator configured to generate a first interpolator clock signal that has a first time delay from the output clock signal and a second phase interpolator configured to generate a second interpolator clock signal that has a second time delay from the output clock signal. The PLL controls a frequency of the output clock signal based on a multiplexing the first interpolator clock signal and the second interpolator clock signal.

Phase locked loop for reducing fractional spur noise

Provided herein is a digital PLL, which can minimize spurious noise. The digital PLL includes a digital controlled oscillator configured to generate an output oscillation signal in response to a digital code, a phase modulation unit configured to perform phase interpolation on the output oscillation signal in response to a phase control code, a TDC configured to generate an error code using a time difference between a reference clock signal and a modulated clock signal, an error detection unit configured to generate a delay code required to compensate for a phase shift error in response to the phase control code and the error code, a delay unit configured to delay at least one of the reference clock signal and the modulated clock signal and provide a delayed clock signal, and a first decoder configured to control the delay unit in response to the delay code.

Digital phase locked loop and method of driving the same

Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal. The phase locked loop (PLL) includes a divider configured to divide the output clock signal to generate a divided clock signal, a time-pulse converter configured to generate a time-pulse conversion signal that has a pulse corresponding to a phase difference between the reference clock signal and the divided clock signal, and a digitally controlled oscillator including an LC resonance circuit for generating the output clock signal and configured to control a frequency of the output clock signal that is determined to correspond to a time constant of the LC resonance circuit according to the time-pulse conversion signal, wherein a sustainment time of changed capacitance is continuously controlled according to a change in the phase difference between the reference clock signal and the divided clock signal.

Phase locked loop and operating method thereof

Disclosed is a digital phase-locked-loop including: a time-to-digital converter (TDC) configured to output a digital bit based on an input clock and a reference clock, in which the TDC includes: a first arbiter group configured to compensate for a phase difference between the input clock and the reference clock with a first average offset and output a first logic value; a second arbiter group configured to compensate for a phase difference between the input clock and the reference clock with a second average offset and output a second logic value; and a signal processor configured to output the digital bit based on the first and second logic values.

Digital phase-locked loop

An embodiment of the present invention relates to a radar apparatus, wherein a distance to a target and a velocity of the target are measured by transmitting a digitally modulated transmitting signal using a digital code and receiving and demodulating an echo signal returned due to reflection of the transmitting signal from the target.

Radar apparatus

Disclosed is a radar apparatus supporting short range and long range radar operations, wherein a plurality of short range transmitting chirp signals and a plurality of long range transmitting chirp signals are generated by a predetermined modulation scheme and is transmitted to an object through at least one transmitting array antenna and signals reflected from the object is received through at least one receiving array antenna, and the plurality of long range transmitting chirp signals have transmission power larger than that for the plurality of short range transmitting chirp signals.

Radar apparatus supporting short and long range radar operation

Provided are a differential voltage-controlled oscillator (VCO) and a quadrature VCO using center-tapped cross-coupling of a transformer. The differential VCO and the quadrature VCO can be driven by low power through a current reuse structure and have an excellent phase noise characteristic by center-tapped cross-coupling through a transformer. Further, variable capacitance units for frequency variation are divided into variable capacitance units for coarse tuning and variable capacitance units for fine tuning. Therefore, it is possible to obtain a wide tuning range while voltage oscillation gain is reduced. Further, the differential VCO and the quadrature VCO are configured in such a manner that the respective variable capacitance units operate linearly throughout the entire capacitance region due to control voltage distribution by resistors. Accordingly, it is possible to obtain a linear control voltage-oscillation frequency characteristic. The quadrature VCO according to the present invention can output four-phase quadrature signals while having an excellent phase noise characteristic, without substrate loss and current consumption caused by the switching transistors.

Differential VCO and quadrature VCO using center-tapped cross-coupling of transformer

A hybrid balun apparatus are disclosed. The hybrid balun apparatus can support both the reception mode and the transmission mode and be advantageous for a high level of integration, by replacing two transformers disposed at a reception path and a transmission path with a single transformer and integrating a T/R switch and a balun into a one chip. Therefore, an IC according to integration extends to a front stage of an antenna to facilitate interfacing between elements, and a burden for designing at a rear stage (i.e., LNA in the reception mode, and PA in the transmission mode) can be reduced.

Hybrid balun apparatus

A frequency calibration loop circuit having a pre-set frequency channel word (FCW) command value, a bit inputted to obtain a target frequency in an oscillator and a pre-set minimum division ratio n (n is a constant) of a programmable divider, includes: an oscillator adjusting an oscillation frequency of an oscillation signal according to a control value; a programmable divider dividing the oscillation signal according to a division ratio to output a divided signal; a counter counting the number of clocks of the divided signal for one cycle of a reference signal to output a count value; and a frequency detector obtaining the control value by subtracting the count value from a reference comparison value, wherein the reference comparison value is obtained by dividing a Frequency Channel Word (FCW) command value by a minimum division ratio of the programmable divider.

Frequency calibration loop circuit

There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result.

Frequency synthesizer including a digital lock detector

Digital lock detector and frequency synthesizer using the same

A wideband low-noise amplifier includes a source-degenerated common-source amplifier, a common-gate amplifier, and a matching frequency band determiner. The source-degenerated common-source amplifier is configured to amplify an input signal to output a first signal that is opposite in phase to the input signal. The common-gate amplifier is connected in parallel to the source-degenerated common-source amplifier to amplify the input signal to output a second signal that has the same phase as the input signal. The matching frequency band determiner is configured to isolate an input terminal of the source-degenerated common-source amplifier and an input terminal of the common-gate amplifier and determine a matching frequency band.

Wideband low-noise amplifier

A coplanar waveguide CPW using multi-layer interconnection CMOS technology is provided. In the CPW including an interlayer insulator disposed on a substrate, metal multilayers disposed on the interlayer insulator, and a ground line-a signal line-a ground line formed of an uppermost metal layer, when a ground line of a lowermost layer is connected to the ground line of the uppermost layer, intermediate metal layers are designed to gradually increase or decrease in width, or to be uneven so as to maximize an area where an ultra-high frequency spreads, thereby minimizing CPW loss and maximizing a slow wave effect. As a result, it is possible to improve performance of an ultra-high frequency circuit and miniaturize the circuit.

Multi-metal coplanar waveguide

Growing community of inventors

Daejeon, South Korea

Cheon Soo Kim