Samsung Electronics Co., Ltd.

Cheon-Oh Lee

Tae-Pyeong Kim

Han-Kyul Lim

Jong-Seok Kim

Nam-Hyun Kim

Ho-Bin Song

Sung-Jun Kim

Ki-hong Kim

Jin-Ho Oh

Jung-Myung Choi

A digital duty cycle correction circuit includes a duty cycle controller and a digital duty control code generator. The duty cycle controller generates first and second output clock signals by compensating duty cycles of first and second input clock signals based on a digital duty control code. The digital duty control code generator generates the digital duty control code based on a frequency value obtained by converting duty cycle information of the first output clock signal and the second output clock signal.

Digital duty cycle correction circuit

Provided is a semiconductor device for compensating for an internal skew without training with an external device. The semiconductor device includes a signal generating unit configured to generate and output a reference signal, a first receiving unit configured to receive the reference signal and output a first output signal, a second receiving unit configured to receive the reference signal and output a second output signal, a delay unit configured to delay the first output signal by a certain time and output a delayed signal, a sampling unit configured to sample the second output signal based on the delayed signal and output sampling data, and a skew controlling unit configured to control the delaying unit based on the sampling data.

Semiconductor device compensating for internal skew and operating method thereof

A data processing device includes a clock converter, a data converter, and an error detector. The clock converter is configured to receive a first clock signal, convert the first clock signal into a second clock signal, and output the second clock signal. The data converter is configured to receive first data, convert the first data into second data using the second clock signal, and output the second data. The error detector is configured to check whether the first clock signal is in a first clock state or a second clock state upon the first data transitioning to a first data state, and output an enable signal to the clock converter upon determining that the first clock signal has transitioned to the first clock state from the second clock state.

Data processing device and method

A transmission circuit includes a serial clock generator, a serializer and a transmission clock generator. The serial clock generator generates a serial clock. The serializer serializes N-bit parallel data to N-bit serial data in synchronization with the serial clock. The transmission clock generator receives the serial clock to generate a transmission clock that has a same delay as the N-bit serial data, and the data transmission circuit simultaneously transmits the N-bit serial data and the serial clock.

Data transmission circuits and data transceiver systems

A short pulse rejection circuit may include an edge detector, a filter circuit, a comparison circuit, and a gating circuit. The edge detector may delay an input signal to generate a delayed input signal, and detect an edge of the input signal to generate an edge detection signal. The filter circuit may perform a low pass filtering on the edge detection signal to generate a first signal. The comparison circuit may compare the first signal with a reference voltage. The gating circuit may gate the delayed input signal based on an output signal of the comparison circuit. Therefore, the short pulse rejection circuit may have a sufficient setup/hold time margin of a flip-flop, and may sample an input signal even when a state of the input signal does not change during an initial operation.

Short pulse rejection circuit and method thereof

A semiconductor memory device including a trimmed voltage generator and a method of generating a trimmed voltage in the semiconductor memory device, in which the semiconductor memory device includes a voltage trimming unit, memory cell array, and a trimming current generator. The voltage trimming unit outputs a first trimming current control signal corresponding to a difference between a predetermined internal voltage and an external voltage supplied from outside of the semiconductor memory device in a trimming mode. The memory cell array stores the first trimming current control signal in the trimming mode and outputs a second trimming current control signal corresponding to the first trimming current control signal in a normal mode. The trimming current generator outputs a trimming current corresponding to the first trimming current control signal in the trimming mode and outputs a trimming current corresponding to the second trimming current control signal in the normal mode. The voltage trimming unit controls the internal voltage to be identical to the external voltage and outputs the controlled internal voltage as the trimmed voltage in response to the trimming current. The semiconductor memory device and the trimmed voltage generating method can output an accurate trimmed voltage without using a voltage supplied from outside in the normal operation.

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Cheonan-si, South Korea

Cheon-Oh Lee