Samsung Electronics Co., Ltd.

Samsung Sdi Co., Inc.

Cheolhong Kim

Seokwoo Nam

Joon-Soo Park

Joonsoo Park

Kukhan Yoon

Jongchul Park

Chul-Ho Kim

Joon Hyuk Kim

Woojin Jung

JungWoo Seo

Byeongsoo Kim

Hunkook Lee

Taehong Min

KyoungRyul Yoon

Junsub Lee

Yongjik Park

Sang-Ho Yun

Pilgoo Jun

Youngcheol Sim

Seunghak Park

Sihyun Kim

Yongju Jung

Un Jeon

A semiconductor memory device includes stacks on a substrate, each of the stacks including word lines stacked on the substrate and first and second string selection lines laterally spaced apart from each other, vertical pillars passing through the stacks, and first and second bit lines extending longitudinally in a first direction and alternatingly arranged in a second direction crossing the first direction. In a plan view, at least two adjacent ones of the first bit lines in the second direction and at least one of the second bit lines overlap each vertical pillar. A distance between a center of the vertical pillar and one of the first bit lines is different from that between the center of the vertical pillar and another of the first bit lines.

Semiconductor memory device

Provided are methods of generating and revising overlay correction data, a method of performing a photolithography process using the overlay correction data, and a method of performing a photolithography process while revising the overlay correction data. The method of revising the overlay correction data includes forming a plurality of overlay keys on a first set of wafers using first overlay correction data, measuring first overlay keys formed on first overlay coordinates in a first shot area of a first wafer among the first set of wafers, generating first overlay error data, and revising primarily the first overlay correction data using the first overlay error data, measuring second overlay keys formed on second overlay coordinates in a second shot area of a second wafer among the first set of wafers, generating second overlay error data, and revising secondarily the primarily revised first overlay correction data using the second overlay error data, and measuring third overlay keys formed on third overlay coordinates in a third shot area of a third wafer among the first set of wafers, generating third overlay error data, revising tertiarily the secondarily revised first overlay correction data, and generating second overlay correction data. The first overlay coordinates, the second overlay coordinates, and the third overlay coordinates are mutually exclusive.

Methods of revising overlay correction data

A web thickness measuring equipment and a method of measuring a web thickness. A web thickness measuring equipment includes: a roller that is rotatable and configured to wind a web; a detection unit that detects a light amount on an outer circumferential surface of the roller or an external surface of the web wound on the roller, and detects a magnetic field of an internal surface of the web opposite to the external surface; and a processor unit configured to obtain a thickness of the web by generating profile data of the outer circumferential surface of the roller, generating displacement amount data of a target external surface of the web, generating displacement amount data of a target internal surface of the web, and comparing the displacement amount data of the target external surface of the web with the displacement amount data of the target internal surface of the web.

Web thickness measuring equipment and method of measuring thickness of a web

A method of forming a semiconductor device includes first preliminary holes over an etch target, the first preliminary holes arranged as a plurality of rows in a first direction, forming dielectric patterns each filling one of the first preliminary holes, sequentially forming a barrier layer and a sacrificial layer on the dielectric patterns, forming etch control patterns between the dielectric patterns, forming second preliminary holes by etching the sacrificial layer, each of the second preliminary holes being in a region defined by at least three dielectric patterns adjacent to each other, and etching the etch target layer corresponding to positions of the first and second preliminary holes to form contact holes.

Methods of forming a semiconductor device

Methods of forming fine patterns are provided. The methods may include forming first hard mask patterns extending in a first direction on a lower layer, forming second hard mask patterns filling gap regions between the first hard mask patterns, forming first mask patterns extending in a second direction perpendicular to the first direction on the first and second hard mask patterns, etching the first hard mask patterns using the first mask patterns as etch masks to form first openings, forming second mask patterns filling the first openings and extending in the second direction, and etching the second hard mask patterns using the second mask patterns as etch masks to form second openings spaced apart from the first openings in a diagonal direction with respect to the first direction.

Methods for forming fine patterns of a semiconductor device

A method may include forming first hard mask patterns and second hard mask patterns extending in a first direction and repeatedly and alternately arranged on a lower layer, forming third mask patterns extending in a second direction perpendicular to the first direction on the first and second hard mask patterns, etching the first hard mask patterns using the third mask patterns to form first openings, forming filling patterns filling the first openings and gap regions between the third mask patterns, forming spacers on both sidewalls of each of the filling patterns, after removing the third mask patterns, and etching the second hard mask patterns using the filling patterns and the spacers to form second openings.

Growing community of inventors

Yongin-si, South Korea

Cheolhong Kim