Samsung Electronics Co., Ltd.

Samsung Display Co., Ltd.

Sungkyunkwan University

Sk Planet Co., Ltd.

Cheol Su Kim

Sang-Ho Shin

Ho-Young Song

Kyo-Min Sohn

Sang-Joon Hwang

Dong-hyun Sohn

Jung-Sik Kim

Jung-Bae Lee

Jung-bae Lee

Kee-Won Kwon

Jun-phyo Lee

Sang-kyun Park

Young-Il Lim

Rak-Joo Sung

Sung-Gi Ahn

Jung Hun Lee

Young-Soo Sohn

Tae-Young Oh

Youn Joon Kim

Dong-Hyuk Lee

Joo-sun Choi

Jang Doo Lee

Sang Jo Lee

Doo-Gon Kim

Hee Jeong Kim

Kyung Min Choi

Tae-seong Jang

Sung-Min Yim

Su-Yeon Doo

Chan-yong Lee

Se Myung Kwon

Jung Sik Kim

Yoon Jee Shin

Hyun-Suk Kang

Ju Suck Lee

Yun Sang Lee

Young Kuk Kim

Ji-Su Min

Min Kyo Shin

Hwa Yeon Lee

Duk Young Kim

Geun-tae Park

Yu Ri Oh

The present disclosure relates to a display substrate. The display substrate may include a substrate, a first lower gate electrode, an insulation pattern, a first insulation layer, and a first active pattern. The first lower gate electrode may be disposed on the substrate. The insulation pattern may be disposed on and patterned to correspond to the first lower gate electrode and may include a silicon nitride. The first insulation layer may be disposed on the insulation pattern and may include a silicon oxide. The first active pattern may be on the first insulation layer and formed of oxide semiconductor and may include a first channel region overlapping the first lower gate electrode and a first wiring region disposed on a side of the first channel region.

Display substrate and display device including the same

Provided are an apparatus for managing customer information, a method for managing customer information, a system for managing customer information, and a non-transitory computer readable storage medium having a computer program recorded thereon. That is, customer identification information may be transmitted to a customer managing apparatus through a customer identification information receiving apparatus positioned in the store. The customer managing apparatus may transmit customer management information corresponding to the customer identification information to a store managing apparatus in the store and user equipment of a clerk. The customer may be managed in the store based on the customer management information. Therefore, it is possible to indirectly acquire customer information from the customer and properly provide required information to the customer.

Apparatus for managing customer information, method for managing customer information, system for managing customer information and non-transitory computer readable storage medium having a computer program recorded thereon

A ternary content addressable memory (TCAM) device includes a memory cell. The memory cell includes a data storage circuit, a limiter circuit, and a discharge circuit. The data storage circuit includes a first resistor and a second resistor connected in series to divide a voltage corresponding to search data, and configured to store cell data. The limiter circuit is configured to receive the divided voltage through an input terminal and transmit an output voltage through an output terminal based on a level of the divided voltage. The discharge circuit discharges a matching line indicating whether the stored cell data matches with the search data, based on the output voltage of the limiter circuit.

TCAM device and operating method thereof

A memory device includes a storage circuit, a first driving circuit, and a second driving circuit. The storage circuit stores first data and compares the first data and second data. The first driving circuit selectively drives a matching line to a first logic state, depending on a comparison result of the first data and the second data by the storage circuit. The second driving circuit drives the matching line to a second logic state regardless of the comparison result.

Memory device driving matching lines according to priority

Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.

Device and method for repairing memory cell and memory system including the device

Provided is a method of refreshing a memory device by controlling a self-refresh cycle according to temperature. In the method, first self-refresh and second self-refresh are performed according to inner temperature of the memory device and a self-refresh cycle is controlled such that an all-bank-refresh (ABR) operation is not performed simultaneously with the start of the second self-refresh. The ABR operation is performed at the start of third self-refresh when the sum of a section of the first self-refresh in which the ABR operation is not performed and a section of the second self-refresh in which the ABR operation is not performed corresponds to a self-refresh cycle.

Refresh method of controlling self-refresh cycle with temperature

Provided is a display device, including a flexible display panel; and a first roller connected to the display panel and having an outer surface, the first roller winding the flexible display panel on the outer surface, the first roller winding both in a first rotating direction and in a second rotating direction opposite to the first direction.

Display device

A memory chip includes a chip input-output pad unit, a plurality of semiconductor dies. The chip input-output pad unit includes a plurality of input-output pins connected to an external device and the plurality of semiconductor dies are connected commonly to the chip input-output pad unit and having a full memory capacity respectively. Each semiconductor die includes a die input-output pad unit, a memory region and a conversion block. The die input-output pad unit includes a plurality of input-output terminals respectively connected to the input-output pins of the chip input-output pad unit. The memory region includes an activated region corresponding to a portion of the full memory capacity and a deactivated region corresponding to a remainder portion of the full memory capacity. The conversion block connects the activated region except the deactivated region to the die input-output pad unit.

Address-remapped memory chip, memory module and memory system including the same

A semiconductor memory device includes a cell array and a refresh controller coupled to the cell array. The refresh controller is configured to insert at least one insertion refresh address in a first refresh address sequence based on address information about the cell array to generate a second refresh address sequence and to apply the second refresh address sequence to the cell array, such that selected cells may be refreshed more frequently without increasing an overall refresh rate.

Semiconductor memory device that controls refresh period, memory system and operating method thereof

A memory device to correct a defect cell generated after packing is performed includes a memory cell array in which a plurality of memory cells are arranged, a repair circuit unit including a first storage unit to store defect cell information in the memory cell array, and a fuse circuit unit including a second storage unit that is programmed according to the defect cell information stored in the first storage unit. The first storage unit includes a volatile memory device, and the second storage unit includes a non-volatile memory device.

Memory device to correct defect cell generated after packaging

A semiconductor memory device having improved refresh characteristics includes a memory array including a plurality of memory cells; a test unit configured to test refresh characteristics of the memory array and generate a first fail address signal; a storage unit configured to store the first fail address signal; and a refresh unit configured to perform a refresh operation on the memory array, wherein the refresh unit is configured to receive the first fail address signal from the storage unit, perform the refresh operation on a first memory cell that does not correspond to the first fail address signal according to a first period, and perform the refresh operation on a second memory cell that corresponds to the first fail address signal according to a second period that is shorter than the first period.

Semiconductor memory device having improved refresh characteristics

A memory device includes an anti-fuse cell array including a plurality of anti-fuse cells. Each anti-fuse cell includes a first cell transistor connected to a common node, a second cell transistor connected to the common node, and an access transistor connected to the common node. The first cell transistor is configured to store data and the second cell transistor is configured to store data when the first cell transistor has defect data.

Anti-fuse circuit and semiconductor device having the same

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Seoul, South Korea

Cheol Su Kim