Samsung Electronics Co., Ltd.

Cheol-Kyu Lee

Kyeong-Koo Chi

Sung-Il Cho

Chang-Jin Kang

Byeong-Yun Nam

Keun-Hee Bai

Makoto Yoshida

Jong-Kyu Kim

Chul Ho Lee

Kyoung-Sub Shin

Seung-Pil Chung

Chang-jin Kang

Joon-Soo Park

Joon-Seok Moon

Seung-Young Son

Kyoung-Ho Jung

Jae-Rok Kahng

Hong Yeon Cho

Young-kyu Cho

Jun-Ho Yoon

Heung-Sik Park

Hye-Jin Jo

A method of fabricating a semiconductor device for reducing a thermal burden on impurity regions of a peripheral circuit region includes preparing a substrate including a cell active region in a cell array region and peripheral active regions in a peripheral circuit region. A cell gate pattern and peripheral gate patterns may be formed on the cell active region and the peripheral active regions. First cell impurity regions may be formed in the cell active region. A first insulating layer and a sacrificial insulating layer may be formed to surround the cell gate pattern and the peripheral gate patterns. Cell conductive pads may be formed in the first insulating layer to electrically connect the first cell impurity regions. The sacrificial insulating layer may be removed adjacent to the peripheral gate patterns. First and second peripheral impurity regions may be sequentially formed in the peripheral active regions adjacent to the peripheral gate patterns.

Method of fabricating semiconductor device for reducing thermal burden on impurity regions of peripheral circuit region

A method of fabricating a semiconductor device is provided. The method can include forming a hard mask film including lower and upper hard mask films on a substrate in which an active region and an isolation region are defined and patterning the hard mask film to provide a hard mask pattern partially exposing the active region and the isolation region. An etchant can be applied to the active and isolation regions using the hard mask pattern as an etching mask to form a trench in the active region of the substrate while avoiding substantially etching the isolation region exposed to the etchant and a gate can be formed on the trench.

Methods of forming semiconductor devices using selective etching of an active region through a hardmask

There are provided a method of forming a fine pattern of a semiconductor device using a silicon germanium sacrificial layer, and a method of forming a self-aligned contact using the same. The method of forming a self-aligned contact of a semiconductor device includes forming a conductive line structure having a conductive material layer, a hard mask layer, and a sidewall spacer on a substrate, and forming a silicon germanium (SiGe) sacrificial layer, which has a height equal to or higher than a height of at least the conductive line structure, on an entire surface of the substrate. Then, a photoresist pattern for defining a contact hole is formed on the sacrificial layer, and the sacrificial layer is dry-etched, thereby forming a contact hole for exposing the substrate. A plurality of contacts for filling the contact hole are formed using polysilicon, and the remained sacrificial layer is wet-etched. Then, the region where the sacrificial layer is removed is filled with silicon oxide, thereby forming a first interlayer insulating layer.

Method of forming fine pattern of semiconductor device using sige layer as sacrificial layer, and method of forming self-aligned contacts using the same

Example embodiments relate to a semiconductor memory device and a method of forming the semiconductor memory device. The semiconductor memory device may include a first interlayer insulating layer on a semiconductor substrate. A bit line may be arranged in a first direction on the first interlayer insulating layer. A bit line contact pad may be disposed in the first interlayer insulating layer and electrically connected to the bit line. A storage contact pad may be disposed in the first interlayer insulating layer. A top surface of the bit line contact pad may be lower than a top surface of the storage contact pad.

Semiconductor memory device and method of forming the same

Method of forming fine pattern of semiconductor device using SiGe layer as sacrificial layer, and method of forming self-aligned contacts using the same

A method of manufacturing a semiconductor memory device includes forming a carbon-containing layer on a semiconductor substrate, forming an insulating layer pattern on the carbon-containing layer, the insulating layer pattern partially exposing an upper surface of the carbon-containing layer, dry-etching the exposed portion of the carbon-containing layer, to form a carbon-containing layer pattern for defining a storage node hole, forming a bottom electrode inside the storage node hole, forming a dielectric layer on the bottom electrode inside the storage node hole, the dielectric layer covering the bottom electrode, and forming an upper electrode on the dielectric layer inside the storage node hole, the upper electrode covering the dielectric layer.

Method of manufacturing a semiconductor memory device

A method of forming a capacitor can include etching a metal-nitride layer in an environment comprising fluorine and oxygen to form a capacitor electrode.

Methods of forming capacitor electrodes using fluorine and oxygen

Methods for etching a metal layer and a metallization method of a semiconductor device using an etching gas that includes Cland Nare provided. A mask layer is formed on the metal layer, the etching gas is supplied to the metal layer, and the metal layer is etched by the etching gas using the mask layer as an etch mask. The metal layer may be formed of aluminum or an aluminum alloy. Cland Nmay be mixed at a ratio of 1:1 to 1:10. The etching gas may also include additional gases such as inactive gases or gases that include the elements H, O, F, He, or C. In addition, Nmay be supplied at a flow rate of from 45&#x2013;65% of the total flow rate of the etching gas, which results in a reduction in the occurrence of micro-loading and cone-shaped defects in semiconductor devices.

Method of etching a metal layer using a mask, a metallization method for a semiconductor device, a method of etching a metal layer, and an etching gas

A method for optimizing a seasoning recipe for a dry etch process. The method includes setting a critical value of reproducibility, a main etch recipe, and a preliminary seasoning recipe. A test wafer is then etched using the preliminary seasoning recipe in a dry etch chamber. Next, a main etch process is performed with respect to at least 10 run wafers in the dry etch chamber using the main etch recipe and an end-point detection time for each wafer is determined. An initial dispersion and a standard deviation are then determined using the determined end-point detection times. The critical value of reproducibility is then compared to the initial dispersion. If the initial dispersion is equal to or less than the critical value of reproducibility, the preliminary seasoning recipe is used as the seasoning recipe, otherwise the preliminary seasoning recipe is modified and the process is repeated until an optimal seasoning recipe is determined.

Method of optimizing seasoning recipe for etch process

A method of etching a material film formed on a semiconductor wafer loaded onto a reaction chamber of a surface wave coupled plasma etching apparatus having an insulation plate which is capable of generating surface waves by microwaves, and a glass plate placed below the insulation plate, for transmitting the produced surface waves. In the method, the glass plate is rapidly pre-heated by generating an argon (Ar) or xenon (Xe) surface wave coupled plasma which has a high ion density and a large mass, and the material layer is then etched. Therefore, the preheating time of the glass plate can be sharply reduced to less than five minutes. Also, because the etching gas is not used for the heating of the glass, damage to the glass plate can be reduced and generation of polymer on the glass plate is suppressed with an improved etching efficiency, so that failure in etching can also be avoided.

Growing community of inventors

Yongin-si, South Korea

Cheol-Kyu Lee