Samsung Electronics Co., Ltd.

Cheol-Hong Park

Hyun-woo Kim

Sang-Seok Kang

Cha-Won Koh

Jin-Kyu Han

Jong-hyun Choi

Sang-Min Park

Sang-seok Kang

Sang-Yoon Woo

Jae-hoon Joo

Example embodiments relate to a method of forming a photoresist pattern and a method of fabricating a semiconductor device using the same. The method of fabricating a semiconductor device comprises forming a mask layer on a substrate, forming a photoresist pattern on the mask layer, the photoresist pattern having pattern portions at a first height and recess portions, applying a first liquid onto the photoresist pattern, filling the recess portions with a pattern filler at a second height, the pattern filler having an higher etch rate than the etch rate of the pattern portions to the same etchant, removing the first liquid, etching the pattern filler after removing the first liquid, etching the mask layer via the photoresist pattern to form a mask pattern, and etching the substrate via the mask pattern to form a fine pattern.

Method of forming photoresist pattern and method of fabricating semiconductor device using the same

In a method of forming a pattern, a lower coating layer and a photoresist layer are sequentially formed on an object layer. An exposure process may be performed such that the photoresist layer is divided into an exposed portion and a non-exposed portion. A portion of the lower coating layer overlapping or contacting the exposed portion is at least partially transformed into a polarity conversion portion that has a polarity substantially identical to that of the exposed portion. The non-exposed portion of the photoresist layer is selectively removed.

Methods of forming patterns using photoresists

A test apparatus for a semiconductor memory device applies a test input pattern to the semiconductor memory device to produce a test output pattern. The test apparatus compares the test output pattern to an expected output pattern using a plurality of comparators to determine whether the semiconductor memory device is defective. The plurality of comparators are respectively controlled by a respective plurality of strobe signals having relative phase delays so that the test output pattern is compared to the expected output pattern at different times.

Test apparatus for semiconductor memory device

A signal generating circuit of a semiconductor device comprises n input test pins for receiving respective coded input signals. At least one of the input signals is coded in more than two possible levels, such as 3 levels or four levels. The device also includes an indicator I/O signal generators, each coupled respectively with an associated input test pin. Each indicator signal generator generates two-level indicator signals in response to the coded input signal received by its associated input test pin. A decoder receives the indicator signals to produce decoded signals, and a mode selecting circuit generates mode selecting signals with the decoded signals responsive to mode setting signals. Each indicator signal generators outputs a regular signal when the input test signal is an ordinary low, a control signal when the input test signal is an ordinary high, and a higher first level signal when the input test signal is a super high. If more than three levels are used, the indicator signal generator further generates corresponding signals for these higher values.

Test signal generating circuit of a semiconductor device with pins receiving signals of multiple voltage levels and method for invoking test modes

An integrated circuit includes first and second pads that are electrically connected to a circuit inside the integrated circuit. The circuit performs multiple functions which may be selected. A function identification circuit, inside the integrated circuit, is electrically connected to the first and second pads. The function identification circuit operates in multiple modes, wherein each operating mode corresponds to a function performed by the circuit. The function of the circuit may thereby be identified using fewer pads which may allow a reduction in the cost of the integrated circuit.

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Seoul, South Korea

Cheol-Hong Park