Integrated Device Technology, Inc.

Renesas Electronics America Inc.

Silicon Spread Corporation

Chenxiao Ren

Shwetal Arvind Patel

Tao Jing

Alejandro F Gonzalez

Yongmin Ge

Andy Zhang

Wen Jie Meng

Yue Wang

Juan Qiao

Zhongyuan Chang

Shubing Zhai

David Chang

Xudong Shi

Arvind Shweta Patel

An apparatus includes a power management integrated circuit (PMIC). The PMIC includes a voltage regulator supplied by a first power source and configured to generate a first output and a charge pump supplied by a second power source and configured to generate a second output. A bias voltage output of the power management integrated circuit is generated based at least in part on the first output and the second output. The charge pump is configured to adjust the second output based at least in part on a comparison between the bias voltage output and a reference voltage.

Power management integrated circuit with charge pump

In an embodiment, an apparatus is disclosed that includes a power management integrated circuit (PMIC). The PMIC includes a voltage regulator supplied by a first power source and configured to generate a first output and a charge pump supplied by a second power source and configured to generate a second output. A bias voltage output of the power management integrated circuit is generated based at least in part on the first output and the second output. The charge pump is configured to adjust the second output based at least in part on a comparison between the bias voltage output and a reference voltage.

An apparatus includes a plurality of registers and a host interface comprising a plurality of pins. One of the plurality of registers may be a power state entry register configured to control entry to a low power state. One of the plurality of pins may be an enable pin. The apparatus may be configured to enter the low power state in response to setting the power state entry register to a first value and providing the enable pin a signal with a first level. The apparatus may be configured to exit the low power state in response to providing the enable pin the signal with a second level. The apparatus may enter an idle state after exiting the low power state. The low power state may consume less power than the idle state. The enable pin is implemented as an input configured to control a status of a plurality of regulators.

DDR5 client PMIC power up sequence and state transitions

An apparatus including a host interface and a registered clock driver interface. The host interface may be configured to receive an enable command from a host. The registered clock driver interface may be configured to perform power management for a dual in-line memory module, generate data for the dual in-line memory module, communicate the data, receive a clock signal and communicate an interrupt signal. The registered clock driver interface may be disabled at power on. The registered clock driver interface may be enabled by in response to the enable command. The apparatus may be implemented as a component on the dual in-line memory module.

DDR5 RCD interface protocol and operation

An apparatus including a host interface and a power management interface. The host interface may be configured to receive control words from a host. The power management interface may be configured to (i) enable the host to read/write data from/to a power management circuit of a dual in-line memory module, (ii) communicate the data, (iii) generate a clock signal and (iv) communicate an interrupt signal. The power management interface is disabled at power on. The apparatus is configured to (i) decode the control words, (ii) enable the power management interface when the control words provide an enable command and (iii) perform a response to the interrupt signal. The clock signal may operate independently from a host clock.

DDR5 PMIC interface protocol and operation

An apparatus including a first circuit and a second circuit. The first circuit may generate an output signal with a regulated voltage and maintain a constant switch frequency having a first on time and a first off time. The second circuit may generate a shifted signal based on a phase delay with respect to the output signal and maintain a shifted frequency having a second on time and a second off time. The second on time may follow the first on time by the phase delay. The second on time may be based on the first on time and transient conditions of a load. The apparatus may implement an automatic phase shift adjustment. A current sensing comparison may implement a cycle-by-cycle comparison between the output signal and the shifted signal to determine the second on time and perform a tuning operation to achieve inductor current balancing.

Auto-phase-shifting and dynamic on time control current balancing multi-phase constant on time buck converter

An apparatus comprising an input interface, an output interface and an adjustment circuit. The input interface may comprise a plurality of input stages each configured to receive a data signal and a clock signal and present an intermediate signal. The output interface may comprise a plurality of output stages each configured to receive the intermediate signal, receive an adjusted clock signal and present an output signal. The adjustment circuit may comprise a plurality of adjustment components each configured to (i) receive the clock signal and (ii) present the adjusted clock signal. The clock signal may be presented through a clock tree. The adjustment circuit may be located near the output interface. The adjustment circuit may be configured to resynchronize the clock signal for each bit transmitted to reduce a mismatch between a bit to bit delay and a delay caused by the clock tree.

Resynchronization of a clock associated with each data bit in a double data rate memory system

A charging system for a mobile device includes a transmitter and a receiver. The transmitter includes (a) a first interface to a power source; (b) a second interface to the receiver; (c) a polarity detection circuit for detecting polarities of the; and (d) first and second switches controlled by the polarity detection circuit, wherein each switch selectively connects a terminal of the first interface to a terminal of the second interface. The receiver includes: (a) a first interface; (b) a second interface coupled to a device to be charged; and (c) a connection circuit between a terminal of the first interface and a terminal of the second interface, wherein the connection circuit is conductive when the voltage across these terminals is of a first polarity, and a second polarity otherwise.

Wireless charger circuit and method

An apparatus includes an adjustable oscillator circuit configured to generate an output signal having a frequency that varies responsive to a frequency control signal and a frequency reference generator circuit configured to produce a frequency reference signal. The apparatus further includes a calibration circuit configured to determine a relationship of the output signal to the frequency reference signal and to enable and disable the frequency reference generator circuit based on the determined relationship.

Frequency synthesizers with dynamic calibration intervals

A method and apparatus for analog smooth switch in VCO loading control, in one technique, receiving an input signal to adjust a frequency of an oscillator; activating one or more switches to control a current source/sink based on the received input signal; applying the current source/sink to a capacitor to adjust a voltage on the capacitor; and applying the voltage on the capacitor to one or more switches, each of the one or more switches connected between a load and a stage of the oscillator.

Method and apparatus for analog smooth switch in VCO loading control

A clock generator includes a phase-lock loop for generating an output clock signal based on a reference clock signal. The phase-lock loop includes a charge pump, a low-pass filter, and a self-bias circuit. The low-pass filter generates a bias voltage and the self-bias circuit generates a charge current based on the bias voltage. The charge pump generates an output based on the charge current to maintain a constant open-loop bandwidth of the phase-lock loop.

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Fremont, CA, United States of America

Chenxiao Ren