Infineon Technologies Ag

Other

International Business Machines Corporation

Siemens Aktiengesellschaft

Chenting Lin

Jingyu Lian

Nicolas Nagel

Michael Lester Wise

Andreas Knorr

Horatio Seymour Wildman

Maria Ronay

Hua Shen

Jenny Lian

Florian Schnabel

Sumit Pandey

Robert Ploessl

Robert Van Den Berg

Lawrence Alfred Clevenger

Katherine Lynn Saenger

Kenneth Parker Rodbell

Yun-Yu Wang

Rajarao Jammy

Kwong Hon Wong

David Edward Kotecki

John A Miller

Jeremy K Stephens

Roy Charles Iggulden

Karl E Boggs

Ronald J Schutz

Larry Clevenger

Stefan Weber

Keith K Wong

Nicholas Nagel

Lee J Kimball

Ranier Florian Schnabel

Joachim F Nuetzel

An interconnect includes an opening formed in a dielectric layer. A conductive barrier is deposited in the opening, over which a first conductive layer is deposited. A conductive oxide is deposited over the first conductive layer, and a second conductive layer, formed from the same material as the first conductive layer, is deposited over the conductive liner.

Multi-layer electrode and method of forming the same

A two-step chemical mechanical polishing (CMP) process is provided to minimize (reduce) dishing of metal lines in trenches in an insulation (oxide) layer of each of a plurality of semiconductor wafers during fabrication thereof. For each wafer, the first step involves CMP of a metal layer disposed on the oxide layer and having a lower portion located in the trenches for forming metal lines and an upper portion overlying the lower portion. The first step polishing uses a first polishing pad to remove the bulk of the metal layer upper portion while generating concomitant CMP residue, and leaves a minimized (reduced) remainder of the metal layer upper portion without dishing of the metal layer lower portion in the trenches. The second step continues the CMP with a second polishing pad to remove the remainder of the metal layer upper portion with minimized (reduced) dishing of the metal layer lower portion to an extent providing the metal lines as individual metal lines in the trenches. Each wafer undergoes the first step polishing with the first polishing pad and then the second step polishing with the second polishing pad. The second polishing pad has at most a deficient content of prior accumulated concomitant CMP residue, e.g., is a relatively fresh (clean) polishing pad.

Metal chemical polishing process for minimizing dishing during semiconductor wafer fabrication

A multi-layer electrode ( ) and method of fabrication thereof in which a conductive region ( ) is separated from a barrier layer ( ) by a first conductive liner ( ) and a second conductive liner ( ). First conductive layer ( ) comprises Pt, and second conductive liner ( ) comprises a thin layer of conductive oxide. The multi-layer electrode ( ) prevents oxygen diffusion through the top conductive region ( ) and reduces material variation during electrode patterning.

Multi-layer Pt electrode for DRAM and FRAM with high K dielectric materials

Improved CMP uniformity is achieved by providing improved control of the slurry distribution. Improved slurry distribution is achieved by, for example, the use of a slurry dispenser that dispenses slurry from a plurality of dispensing points. Providing a squeeze bar between the slurry dispenser and wafer to redistribute the slurry also improves the slurry distribution.

CMP uniformity

A method for forming a crystalline dielectric layer deposits an amorphous metallic oxide dielectric layer on a surface. The amorphous metallic oxide dielectric layer is treated with a plasma at a temperature of less than or equal to 400 degrees Celsius to form a crystalline layer.

Methods for crystallizing metallic oxide dielectric films at low temperature

A method of forming an integrated barrier/contact for stacked capacitors is provided which results in reduced cost of ownership and in a barrier which is nominally several times thicker than convention structures. The resulting structure results in decreased contact plug resistance as compared with conventional devices.

Method for forming an integrated barrier/plug for a stacked capacitor

A method of enriching the surface of a substrate with a solute material that was originally dissolved in the substrate material, to yield a uniform dispersion of the solute material at the substrate surface. The method generally entails the use of a solvent material that is more reactive than the solute material to a chosen reactive agent. The surface of the substrate is reacted with the reactive agent to preferentially form a reaction compound of the solvent material at the surface of the substrate. As the compound layer develops, the solute material segregates or diffuses out of the compound layer and into the underlying substrate, such that the region of the substrate nearest the compound layer becomes enriched with the solute material. At least a portion of the compound layer is then removed without removing the underlying enriched region of the substrate. For microcircuit applications, the method can be used to enrich the surface of an aluminum line with elemental copper to improve the electromigration resistance of the line.

Method of forming a solute-enriched layer in a substrate surface and article formed thereby

A capacitor structure that comprises a top platinum electrode and a bottom electrode having insulator on the sidewalls of the electrodes, and wherein the bottom electrode is from depositing a first electrode portion being recessed with respect to the insulator on the sidewalls thereof and depositing a second insulator portion is provided.

Capacitor stack structure and method of fabricating description

A process is provided for planarization of an insulation layer, e.g., of silicon dioxide, on a semiconductor wafer, e.g., of silicon, and having a surface with a downwardly stepped chemically mechanically polished arrangement of metal lines in the insulation layer between intervening insulation portions. A first pattern portion of metal lines is separated by intervening insulation portions and defines a first pattern factor having a first value, and an adjacent second pattern portion of metal lines is separated by intervening insulation portions and defines a second pattern factor having a second value different from the first value. The second pattern portion is at a step depth relative to the insulation layer surface different from that of the first pattern portion relative to such layer surface. The process involves chemically mechanically polishing the insulation layer surface and first and second pattern portions to reduce the step depths of the pattern portions relative to the insulation layer surface and to each other, for planarizing the insulation layer surface and pattern portions relative to each other. The process further involves providing a further insulation layer on the planarized insulation layer, and a further arrangement of metal lines in the further insulation layer, and chemically mechanically polishing the further arrangement of metal lines.

Planarization after metal chemical mechanical polishing in semiconductor wafer fabrication

A stacked capacitor, in accordance with the present invention includes a conductive plug disposed within a trench for connecting to an access device. A barrier is formed on the plug and is disposed within the trench. A dielectric layer is formed over the trench, the dielectric layer forming a hole therethrough exposing at least a portion of the barrier. A first electrode is formed within the hole and extends from the hole. A capacitor dielectric layer is formed on the first electrode and separating the first electrode from a second electrode, and the dielectric layer and the first electrode substantially prevent chemical interactions between materials of the barrier and materials of the capacitor dielectric layer and an oxidizing environment used to form the capacitor dielectric layer. A method of fabrication is also included.

Extended trench for preventing interaction between components of stacked capacitors

In accordance with the present invention, a method is disclosed for releasing semiconductor wafers from a polishing pad. The method includes the steps of applying a slurry to a polishing pad, rotating the polishing pad having slurry thereon while applying pressure against a wafer such that the wafer is polished by the slurry, introducing water to the polishing pad, increasing the rotational speed of the polishing pad to remove a portion of the slurry, decreasing the pressure during the step of increasing rotational speed to substantially prevent further polishing and removing the wafer from the polishing pad.

Method of enhancing semiconductor wafer release

The method of polishing metal layers on wafers comprises the steps of: providing indicator areas on said wafer, said indicator areas having combinations of line widths and pattern factors violating existing ground rules of metal lines thereby said indicator areas being dished out during said polishing using a chemical-mechanical polisher to polish the metal layers to remove material therefrom, inspecting indicator areas on the wafer to determine an amount of material removed from said areas, and adjusting the operation of the chemical-mechanical polisher in response to the inspection of the indicator areas. The indicator areas may include macroblocks comprised of a multitude of individual blocks. The wafer may be inspected by optically identifying the polishing state of to blocks in the macroblock. Additionally, the process may be automated for mass production. A feedback loop to the polisher can be formed where data from optical inspection of macroblocks on a polished wafer can be immediately fed back to the polisher in order to adjust process parameters.

CMP process using indicator areas to determine endpoint

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Poughkeepsie, NY, United States of America

Chenting Lin