Silevo, Inc.

Tesla, Inc.

Solarcity Corporation

Novellus Systems Incorporated

Amprius Technologies, Inc.

Chentao Yu

Jianming Fu

Zheng Xu

Jiunn Benjamin Heng

Jianjun Liang

Peijun Ding

Robert T Rozbicki

Sridhar Karthik Kailasam

Girish Anant Dixit

Jonathan Bornstein

Constantin Ionel Stefan

Douglas Brenton Hayden

Weijie Wang

Wen Wu

Daniel Seo

Guanghua Song

Kenneth Jow

Provided herein are nanostructures for lithium ion battery electrodes and methods of fabrication. In some embodiments, a nanostructure template coated with a silicon-based coating is provided. The silicon coating may include a non-conformal, more porous silicon-rich SiElayer and a conformal, denser SiElayer on the non-conformal, more porous layer. In some embodiments, two different deposition processes are used: a PECVD layer to deposit the non-conformal, silicon-rich SiElayer and a thermal CVD process to deposit the conformal layer. The silicon-rich SiEmaterial prevents silicon crystalline domain growth, limits macroscopic swelling, increases lithium diffusion rate and enhances significantly battery life during lithium ion battery cycle of charge and discharge.

Compositionally modified silicon coatings for use in a lithium ion battery anode

One embodiment of the present invention provides a solar cell. The solar cell includes a substrate, a first heavily doped crystalline-Si (c-Si) layer situated above the substrate, a lightly doped c-Si layer situated above the first heavily doped crystalline-Si layer, a second heavily doped c-Si layer situated above the lightly doped c-Si layer, a front side electrode grid situated above the second heavily doped c-Si layer, and a backside electrode grid situated on the backside of the substrate.

Aluminum grid as backside conductor on epitaxial silicon thin film solar cells

One embodiment of the present invention provides a solar cell. The solar cell includes a Si base layer, a passivation layer situated above the Si base layer, a layer of heavily doped amorphous Si (a-Si) situated above the passivation layer, a first transparent-conducting-oxide (TCO) layer situated above the heavily doped a-Si layer, a back-side electrode situated below the Si base layer, and a front-side electrode situated above the first TCO layer. The first TCO layer comprises at least one of: GaInO, GaInSnO, ZnInO, and ZnInSnO.

Transparent conducting oxide for photovoltaic devices

One embodiment of the present invention provides a photovoltaic module. The photovoltaic module includes an optical concentrator and a tunneling-junction solar cell. The tunneling-junction solar cell includes a base layer, a quantum-tunneling-barrier (QTB) layer situated above the base layer, an emitter layer, a front-side electrode, and a back-side electrode.

Tunneling-junction solar cell with copper grid for concentrated photovoltaic application

One embodiment of the present invention provides a method for fabricating solar cells. During operation, an anti-reflection layer is deposited on top of a semiconductor structure to form a photovoltaic structure, and a front-side electrode grid comprising a metal stack is formed on top of the photovoltaic structure. The metal stack comprises a metal-adhesive layer comprising Ti or Ta, and a conducting layer comprising Cu or Ag situated above the metal-adhesive layer.

Solar cell with electroplated metal grid

One embodiment of the present invention provides a double-sided heterojunction solar cell module. The solar cell includes a frontside glass cover, a backside glass cover situated below the frontside glass cover, and a number of solar cells situated between the frontside glass cover and the backside glass cover. Each solar cell includes a semiconductor multilayer structure situated below the frontside glass cover, including: a frontside electrode grid, a first layer of heavily doped amorphous Si (a-Si) situated below the frontside electrode, a layer of lightly doped crystalline-Si (c-Si) situated below the first layer of heavily doped a-Si, and a layer of heavily doped c-Si situated below the lightly doped c-Si layer. The solar cell also includes a second layer of heavily doped a-Si situated below the multilayer structure; and a backside electrode situated below the second layer of heavily doped a-Si.

Low-cost high-efficiency solar module using epitaxial Si thin-film absorber and double-sided heterojunction solar cell with integrated module fabrication

One embodiment of the present invention provides a photovoltaic module. The photovoltaic module includes an optical concentrator and a tunneling-junction solar cell. The tunneling junction solar cell includes a base layer, a quantum-tunneling-barrier (QTB) layer situated above the base layer, an emitter layer, a front-side electrode, and a back-side electrode.

One embodiment of the present invention provides a heterojunction solar cell. The solar cell includes a metallurgical-grade Si (MG-Si) substrate, a layer of heavily doped crystalline-Si situated above the MG-Si substrate, a layer of lightly doped crystalline-Si situated above the heavily doped crystalline-Si layer, a backside ohmic-contact layer situated on the backside of the MG-Si substrate, a passivation layer situated above the heavily doped crystalline-Si layer, a layer of heavily doped amorphous Si (a-Si) situated above the passivation layer, a layer of transparent-conducting-oxide (TCO) situated above the heavily doped a-Si layer, and a front ohmic-contact electrode situated above the TCO layer.

Heterojunction solar cell based on epitaxial crystalline-silicon thin film on metallurgical silicon substrate design

One embodiment of the present invention provides a tunneling junction based solar cell. The solar cell includes a base layer; a quantum-tunneling-barrier (QTB) layer situated adjacent to the base layer; an emitter; a surface field layer; a front-side electrode; and a back-side electrode.

Solar cell with oxide tunneling junctions

One embodiment of the present invention provides a method for fabricating a solar cell. The method includes: melting a metallurgical-grade (MG) Si feedstock, lowering a single-crystalline Si seed to touch the surface of the molten MG-Si, slowly pulling out a single-crystal Si ingot of the molten MG-Si, processing the Si ingot into single crystal Si wafers to form MG-Si substrates for subsequent epitaxial growth, leaching out residual metal impurities in the MG-Si substrate, epitaxially growing a layer of single-crystal Si thin film doped with boron on the MG-Si substrate, doping phosphor to the single-crystal Si thin film to form an emitter layer, depositing an anti-reflection layer on top of the single-crystal Si thin film, and forming the front and the back electrical contacts.

Solar cells fabricated by using CVD epitaxial Si films on metallurgical-grade Si wafers

One embodiment of the present invention provides a solar cell. The solar cell includes a metallurgical-grade Si (MG-Si) substrate, a first layer of heavily doped crystalline-Si situated above the MG-Si substrate, a layer of lightly doped crystalline-Si situated above the first heavily doped crystalline-Si layer, a backside ohmic-contact layer situated on the backside of the MG-Si substrate, a second layer of heavily doped crystalline-Si situated above the lightly doped crystalline-Si layer, a first layer of dielectric situated above the second heavily doped crystalline-Si layer, a second layer of dielectric situated above the first dielectric layer, and front electrodes situated above the second dielectric layer.

Silicon-based dielectric stack passivation of Si-epitaxial thin-film solar cells

Methods of resputtering material from the wafer surface include at least one operation of resputtering material under a pressure of at least 10 mTorr. The methods can be used in conjunction with an iPVD apparatus, such as hollow cathode magnetron (HCM) or planar magnetron. The resputtered material may be a diffusion barrier material or a conductive layer material. The methods provide process conditions which minimize the damage to the dielectric layer during resputtering. The methods allow considerable etching of the diffusion barrier material at the via bottom, while not damaging exposed dielectric elsewhere on the wafer. Specifically, they provide a solution for the dielectric microtrenching problem occurring during conventional resputter process. Furthermore, the methods increase the etch rate to deposition rate ratio (E/D) and improve the etch back nonuniformity (EBNU) of resputter process. In general, the methods provide IC devices with higher reliability and decrease wafer manufacturing costs.

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Sunnyvale, CA, United States of America

Chentao Yu