Massachusetts Institute of Technology

Chenson K Chen

Rabindra N Das

Donna-Ruth Webb Yost

Mark A Gouker

Craig L Keast

Keith Warner

Steven A Vitale

Bor-Yeu Tsaur

James Im

A multi-layer semiconductor device includes at least a first semiconductor structure and a second semiconductor structure, each having first and second opposing surfaces. The second semiconductor structure includes a first section and a second section, the second section including a device layer and an insulating layer. The second semiconductor structure also includes one or more conductive structures and one or more interconnect pads. Select ones of the interconnect pads are electrically coupled to select ones of the conductive structures. The multi-layer semiconductor device additionally includes one or more interconnect structures disposed between and coupled to select portions of second surfaces of each of the first and second semiconductor structures. A corresponding method for fabricating a multi-layer semiconductor device is also provided.

Semiconductor structures for assembly in multi-layer semiconductor devices including at least one semiconductor structure

A semiconductor structure includes at least two substrate layers, each of the at least two substrate layers having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The semiconductor structure also includes a substrate joining layer disposed between and coupled to the second surface of a first one of the at least two substrate layers and the first surface of a second one of the at least two substrate layers. The substrate joining layer includes at least one integrated circuit (IC) structure disposed between the first and second surfaces of said substrate joining layer. A corresponding method for fabricating a semiconductor structure is also provided.

Interconnect structures for assembly of semiconductor structures including at least one integrated circuit structure

A multi-layer semiconductor device includes at least two semiconductor structures, each of the at least two semiconductor structures having first and second opposing surfaces and including a first section and a second section. The second section includes a device layer and an insulating layer. The multi-layer semiconductor device also includes one or more conductive structures and one or more interconnect pads. Select ones of the one or more interconnect pads are electrically coupled to the one or more conductive structures. The multi-layer semiconductor device additionally includes a via joining layer disposed between and coupled to second surfaces of each of the at least two semiconductor structures. A corresponding method for fabricating a multi-layer semiconductor device is also provided.

Interconnect structures for assembly of multi-layer semiconductor devices

Wafers of silicon-on-insulator (SOI) produced by the zone melting recrystallization technique are known to exhibit warping and edge defects which prohibit their use in automated silicon wafer processing equipment. These deficiencies arise from excess heat buildup at the periphery of the wafer because the wafer edge acts as a barrier to heat transfer. Dissipation of heat from the edge by varying the heat dissipation efficiency of the environment about the periphery of the wafer allows wafers with substantially fewer defects to be produced.

Edge-heat-sink technique for zone melting recrystallization of

A method is provided for zone-melting-recrystallization (ZMR) to produce high quality substantially subboundary-free silicon-on-insulator (SOI) thin films by controlled radiant heating of the silicon film. Using this technique, a much wider experimental parameter range which improves the uniformity of the crystalline quality over the entire SOI film is possible.

Enhanced radiative zone-melting recrystallization method and apparatus

Edge-heat sink technqiue for zone melting recrystallization of

Wetting of encapsulated silicon-on-insulator (SOI) films during a zone-melting recrystallization (ZMR) process is enhanced by a high temperature anneal of the SOI structure in a reactive nitrogen-containing ambient to introduce nitrogen atoms to the polysilicon/silicon dioxide cap interface. The technique is not only more effective in present in cap fracture and enhancing crystal quality but is also susceptible to batch processing with noncritical parameters in a highly efficient, uniform manner. Preferably, the cap is exposed to 100% ammonia at 1100.degree. C. for one to three hours followed by a pure oxygen purge for twenty minutes. The ammonia atmosphere is reintroduced at the same temperature for another one to three hour period before ZMR. The process is believed to result in less than a half monolayer of nitrogen at the interior cap interface thereby significantly lowering the contact angle and improving the wetting character of the SOI structure.

Capping technique for zone-melting recrystallization of insulated

Wetting of encapsulated silicon-on-insulator (SOI) films during a zone-melting recrystallization (ZMR) process is enhanced by a high temperature anneal of the SOI structure in a reactive nitrogen-containing ambient to introduce nitrogen atoms to the polysilicon/silicon dioxide cap interface. The technique is not only more effective in preventing cap fracture and enhancing crystal quality but it also susceptible to batch processing with noncritical parameters in a highly efficient, uniform manner. Preferably, the cap is exposed to 100% ammonia at 1100.degree. C. for one to three hours followed by a pure oxygen purge for twenty minutes. The ammonia atmosphere is reintroduced at the same temperature for another one to three hour period before ZMR. The process is believed to result in less than a half monolayer of nitrogen at the interior cap interface thereby significantly lowering the contact angle and improving the wetting character of the SOI structure.

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Weston, MA, United States of America

Chenson K Chen