Taiwan Semiconductor Manufacturing Comp. Ltd.

University of California

Actel Corporation, Inc.

National Semiconductor Corporation

Semtech Corporation

National Yang Ming Chiao Tung University

Vlsi Technology, Inc.

Sunrise Memory Corporation

Other

Advanced Micro Devices Corporation

Monolithic System Technology, Inc.

Bta Technology, Inc.

Chenming Hu

Yee-Chia Yeo

Fu-Liang Yang

Wen-Chin Lee

Chun-Chieh Lin

Chien-Chao Huang

Chao-Hsiung Wang

Hao-Yu Chen

Horng-Huei Tseng

Chung-Hu Ge

Chih-Hsin Ko

Kuo-Nan Yang

Chih-Hao Wang

Hsing-Jen Wann

Ping Keung Ko

Mong-Song Liang

Hou-Yu Chen

Liang-Gi Yao

Ping-Wei Wang

Guobiao Zhang

Hsin-Hui Lee

Chung-Hu Ke

Shang-Chih Chen

Yi-Ling Chan

Mansun John Chan

Da-Chi Lin

Chen-Hua Douglas Yu

Bin Yu

Shih-Chang Chen

John L McCollum

Tsu-Jae King

Yen-Ping Wang

Steve S Chiang

Hung-Wei Chen

Abdul R Forouhi

Esmat Z Hamdy

Tien-Chih Chang

You-Lin Chu

Jeffrey T Pohlman

Ya-Chin King

Rita Trivedi

Shin-Puu Jeng

Hao-Yi Tsai

Syun-Ming Jang Jang

Eli Harari

Carlos H Diaz

Prashant Majhi

Pei-Haw Tsao

Nathan W Cheung

Igor Polishchuk

Wu-Yi Henry Chien

Chao-Yuan Su

Chender Huang

Burn-Jeng Lin

Jyh-Chyurn Guo

Hsun-Chih Tsao

Hsien-Kuang Chiu

Chung S Wang

Chuan-Yi Lin

Yi-Hen Wei

Ying T Loh

Shang Y Hou

Haur-Ywh Chen

Fu-Liaog Yang

How-Yu Chen

Pushkar Ranade

Anupama Bowonder

Pratik Patel

Daniel Chou

Xiang Lu

Chun Chich Lin

Yi-Lang Chen

Jhy-Chyum Guo

Ching-Wei Tsai

Leland Chang

Vivek Subramanian

Gregory William Bakker

Fu-Chieh Hsu

Steven Paul Sapp

Min-Hwa Chi

Fang-Cheng Chen

Pin Chia Su

Nguyen Duc Bui

Ta-Wei Wang

Abdelshafy A Eltoukhy

Stephen A Parke

Jeffrey Bokor

Di-Hong Lee

Ping-Kun Wu

Ying K Shum

Reza Moazzami

James C Chen

Wei-Xiang You

Chun Chieh Lin

Scott Zheng

Samuel T Wang

Yang-Kyu Choi

Tim Tsao

Yi-Ling Chang

Howard Chih Hao Wang

A memory circuit includes a memory cell and a source line transistor. The memory cell includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The second transistor and the third transistor form an inverter electrically connected to a drain of the first transistor. The inverter is configured to store two states with different applied voltages. The fourth transistor is electrically connected to a node of the inverter. The source line transistor is electrically connected to the fourth transistor.

Memory circuit and manufacturing method thereof

A thin-film storage transistor includes (a) first and second semiconductor regions comprising polysilicon of a first conductivity; and (b) a channel region between the first and second semiconductor regions, the channel region comprising single-crystal epitaxial grown silicon, and wherein the thin-film storage transistor is formed above a monocrystalline semiconductor substrate.

Epitaxial monocrystalline channel for storage transistors in 3-dimensional memory structures and methods for formation thereof

An integrated circuit structure includes a first transistor, an interconnect structure, a first dielectric layer, polycrystalline plugs, a semiconductor structure and a second transistor. The first transistor is formed on a substrate. The interconnect structure is over the first transistor. The first dielectric layer is over the interconnect structure. The polycrystalline plugs extend from a top surface of the dielectric layer into the dielectric layer. The semiconductor structure is disposed over the first dielectric layer. The second transistor is formed on the semiconductor structure.

Three dimensional integrated circuit and fabrication thereof

A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

Semiconductor device having semiconductor alloy layer adjacent a gate structure

Semiconductor device with silicided source/drain region

Cobalt silicidation process for substrates comprised with a silicon-germanium layer

A three-dimensional (3D) transistor includes a ferroelectric film between the gate and the channel. The 3D transistor can be characterized as a 3D Negative Capacitance (NC) transistor due to the negative capacitance resulting from the ferroelectric film. Performance of the transistor is optimized by manipulating the structure and/or by the selection of materials. In one example, the capacitance of the ferroelectric film (C) is matched to the sum of the gate capacitance (C) and the gate edge capacitance (C), wherein the gate edge capacitance (C) is the capacitance at the edge of the gate and between the gate and the source and its extension, and the gate and the drain and its extension.

3D transistor having a gate stack including a ferroelectric film

Several embodiments of a tunneling transistor are disclosed. In one embodiment, a tunneling transistor includes a semiconductor substrate, a source region formed in the semiconductor substrate, a drain region formed in the semiconductor substrate, a gate stack including a metallic gate electrode and a gate dielectric, and a tunneling junction that is substantially parallel to an interface between the metallic gate electrode and the gate dielectric. As a result of the tunneling junction that is substantially parallel with the interface between the metallic gate electrode and the gate dielectric, an on-current of the tunneling transistor is substantially improved as compared to that of a conventional tunneling transistor. In another embodiment, a tunneling transistor includes a heterostructure that reduces a turn-on voltage of the tunneling transistor.

Tunneling transistor suitable for low voltage operation

A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7&#xb0;) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.

Doping of semiconductor fin devices

A MOSFET includes a gate having a high-k gate dielectric on a substrate and a gate electrode on the gate dielectric. The gate dielectric protrudes beyond the gate electrode. A deep source and drain having shallow extensions are formed on either side of the gate. The deep source and drain are formed by selective in-situ doped epitaxy or by ion implantation and the extensions are formed by selective, in-situ doped epitaxy. The extensions lie beneath the gate in contact with the gate dielectric. The material of the gate dielectric and the amount of its protrusion beyond the gate electrode are selected so that epitaxial procedures and related procedures do not cause bridging between the gate electrode and the source/drain extensions. Methods of fabricating the MOSFET are described.

Ultra-shallow junction MOSFET having a high-k gate dielectric and in-situ doped selective epitaxy source/drain extensions and a method of making same

A structure for an integrated circuit is disclosed. The structure includes a crystalline substrate and four crystalline layers. The first crystalline layer of first lattice constant is positioned on the crystalline substrate. The second crystalline layer has a second lattice constant different from the first lattice constant, and is positioned on said first crystalline layer. The third crystalline layer has a third lattice constant different than said second lattice constant, and is positioned on said second crystalline layer. The strained fourth crystalline layer includes, at least partially, a MOSFET device.

Relaxed silicon germanium substrate with low defect density

An immersion lithographic systemcomprises an optical surface, an immersion fluidwith a pH less than 7 contacting at least a portion of the optical surface, and a semiconductor structurehaving a topmost photoresist layerwherein a portion of the photoresist is in contact with the immersion fluid. Further, a method for illuminating a semiconductor structurehaving a topmost photoresist layercomprising the steps of: introducing an immersion fluidinto a space between an optical surfaceand the photoresist layer wherein the immersion fluid has a pH of less than 7, and directing light preferably with a wavelength of less than 450 nm through the immersion fluid and onto the photoresist.

Immersion fluid for immersion lithography, and method of performing immersion lithography

Growing community of inventors

Hsin-Chu, Taiwan

Chenming Hu